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pluto_hdl_adi/projects/daq2/common/daq2_bd.tcl

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daq2: rebase conflicts
2014-10-22 20:39:17 +00:00
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# dac peripherals
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
ad_ip_instance axi_adxcvr axi_ad9144_xcvr
ad_ip_parameter axi_ad9144_xcvr CONFIG.NUM_OF_LANES 4
ad_ip_parameter axi_ad9144_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_ad9144_xcvr CONFIG.TX_OR_RX_N 1
ad_ip_instance jesd204 axi_ad9144_jesd
ad_ip_parameter axi_ad9144_jesd CONFIG.C_NODE_IS_TRANSMIT 1
ad_ip_parameter axi_ad9144_jesd CONFIG.C_LANES 4
ad_ip_instance axi_ad9144 axi_ad9144_core
ad_ip_parameter axi_ad9144_core CONFIG.QUAD_OR_DUAL_N 0
ad_ip_instance util_upack axi_ad9144_upack
ad_ip_parameter axi_ad9144_upack CONFIG.CHANNEL_DATA_WIDTH 64
ad_ip_parameter axi_ad9144_upack CONFIG.NUM_OF_CHANNELS 2
ad_ip_instance axi_dmac axi_ad9144_dma
ad_ip_parameter axi_ad9144_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_ad9144_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_ad9144_dma CONFIG.ID 1
ad_ip_parameter axi_ad9144_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9144_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9144_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9144_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9144_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9144_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_ad9144_dma CONFIG.DMA_DATA_WIDTH_DEST 128
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# adc peripherals
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
ad_ip_instance axi_adxcvr axi_ad9680_xcvr
ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES 4
ad_ip_parameter axi_ad9680_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9680_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_instance jesd204 axi_ad9680_jesd
ad_ip_parameter axi_ad9680_jesd CONFIG.C_NODE_IS_TRANSMIT 0
ad_ip_parameter axi_ad9680_jesd CONFIG.C_LANES 4
ad_ip_instance axi_ad9680 axi_ad9680_core
ad_ip_instance util_cpack axi_ad9680_cpack
ad_ip_parameter axi_ad9680_cpack CONFIG.CHANNEL_DATA_WIDTH 64
ad_ip_parameter axi_ad9680_cpack CONFIG.NUM_OF_CHANNELS 2
ad_ip_instance axi_dmac axi_ad9680_dma
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad9680_dma CONFIG.ID 0
ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
# shared transceiver core
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
ad_ip_instance util_adxcvr util_daq2_xcvr
ad_ip_parameter util_daq2_xcvr CONFIG.RX_NUM_OF_LANES 4
ad_ip_parameter util_daq2_xcvr CONFIG.TX_NUM_OF_LANES 4
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
ad_connect sys_cpu_resetn util_daq2_xcvr/up_rstn
ad_connect sys_cpu_clk util_daq2_xcvr/up_clk
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
daq2: xcvr pll changes
2016-11-22 17:53:29 +00:00
# reference clocks & resets
create_bd_port -dir I tx_ref_clk_0
create_bd_port -dir I rx_ref_clk_0
projects/- xcvr updates
2016-11-22 21:23:05 +00:00
ad_xcvrpll tx_ref_clk_0 util_daq2_xcvr/qpll_ref_clk_*
ad_xcvrpll rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_*
ad_xcvrpll axi_ad9144_xcvr/up_pll_rst util_daq2_xcvr/up_qpll_rst_*
ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_*
daq2: xcvr pll changes
2016-11-22 17:53:29 +00:00
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# connections (dac)
daq2- xcvr connect
2016-10-06 18:09:27 +00:00
ad_xcvrcon util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd
ad_reconct util_daq2_xcvr/tx_0 axi_ad9144_jesd/gt0_tx
ad_reconct util_daq2_xcvr/tx_1 axi_ad9144_jesd/gt3_tx
ad_reconct util_daq2_xcvr/tx_2 axi_ad9144_jesd/gt1_tx
ad_reconct util_daq2_xcvr/tx_3 axi_ad9144_jesd/gt2_tx
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_core/tx_clk
ad_connect axi_ad9144_jesd/tx_tdata axi_ad9144_core/tx_data
ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_upack/dac_clk
daq2 : Integrate the DACFIFO into the supported projects. + All pack/unpack logic is made by the cpack and upack modules. + The DAC FIFO is integrated between the TX DMA and cpack. + All the top files are updated, all the projects compiled successfully.
2015-05-11 09:17:59 +00:00
ad_connect axi_ad9144_core/dac_enable_0 axi_ad9144_upack/dac_enable_0
ad_connect axi_ad9144_core/dac_ddata_0 axi_ad9144_upack/dac_data_0
daq2- gt changes
2015-08-17 18:11:41 +00:00
ad_connect axi_ad9144_core/dac_valid_0 axi_ad9144_upack/dac_valid_0
daq2 : Integrate the DACFIFO into the supported projects. + All pack/unpack logic is made by the cpack and upack modules. + The DAC FIFO is integrated between the TX DMA and cpack. + All the top files are updated, all the projects compiled successfully.
2015-05-11 09:17:59 +00:00
ad_connect axi_ad9144_core/dac_enable_1 axi_ad9144_upack/dac_enable_1
ad_connect axi_ad9144_core/dac_ddata_1 axi_ad9144_upack/dac_data_1
daq2- gt changes
2015-08-17 18:11:41 +00:00
ad_connect axi_ad9144_core/dac_valid_1 axi_ad9144_upack/dac_valid_1
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_fifo/dac_clk
daq2_common: Fix the dac_rst for DAC FIFO
2017-03-07 14:13:46 +00:00
ad_connect axi_ad9144_jesd_rstgen/peripheral_reset axi_ad9144_fifo/dac_rst
daq2- gt changes
2015-08-17 18:11:41 +00:00
ad_connect axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid
ad_connect axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data
daq2/common: Add util_dacfifo/dac_xfer_out control
2016-03-29 13:55:33 +00:00
ad_connect axi_ad9144_upack/dma_xfer_in axi_ad9144_fifo/dac_xfer_out
daq2- gt changes
2015-08-17 18:11:41 +00:00
ad_connect sys_cpu_clk axi_ad9144_fifo/dma_clk
daq2/common: axi_ad9144_fifo needs a proper reset sequence Connect the axi_ad9144_fifo/dma_rst signal to sys_cpu_reset
2015-06-12 11:03:46 +00:00
ad_connect sys_cpu_reset axi_ad9144_fifo/dma_rst
daq2- gt changes
2015-08-17 18:11:41 +00:00
ad_connect sys_cpu_clk axi_ad9144_dma/m_axis_aclk
ad_connect sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn
ad_connect axi_ad9144_fifo/dma_xfer_req axi_ad9144_dma/m_axis_xfer_req
ad_connect axi_ad9144_fifo/dma_ready axi_ad9144_dma/m_axis_ready
ad_connect axi_ad9144_fifo/dma_data axi_ad9144_dma/m_axis_data
ad_connect axi_ad9144_fifo/dma_valid axi_ad9144_dma/m_axis_valid
ad_connect axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last
daq2 : Integrate the DACFIFO into the supported projects. + All pack/unpack logic is made by the cpack and upack modules. + The DAC FIFO is integrated between the TX DMA and cpack. + All the top files are updated, all the projects compiled successfully.
2015-05-11 09:17:59 +00:00
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# connections (adc)
daq2- xcvr connect
2016-10-06 18:09:27 +00:00
ad_xcvrcon util_daq2_xcvr axi_ad9680_xcvr axi_ad9680_jesd
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk
ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core/rx_sof
ad_connect axi_ad9680_jesd/rx_tdata axi_ad9680_core/rx_data
ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
daq2- xcvr connect
2016-10-06 18:09:27 +00:00
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
daq2 : Integrate the DACFIFO into the supported projects. + All pack/unpack logic is made by the cpack and upack modules. + The DAC FIFO is integrated between the TX DMA and cpack. + All the top files are updated, all the projects compiled successfully.
2015-05-11 09:17:59 +00:00
ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
daq2- xcvr connect
2016-10-06 18:09:27 +00:00
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
daq2 : Integrate the DACFIFO into the supported projects. + All pack/unpack logic is made by the cpack and upack modules. + The DAC FIFO is integrated between the TX DMA and cpack. + All the top files are updated, all the projects compiled successfully.
2015-05-11 09:17:59 +00:00
ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk
ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
daq2- gt changes
2015-08-17 18:11:41 +00:00
ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# interconnect (cpu)
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
ad_cpu_interconnect 0x44A60000 axi_ad9144_xcvr
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
ad_cpu_interconnect 0x44A00000 axi_ad9144_core
ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9144_dma
daq2- spi+xcvr address conflict
2016-08-04 14:50:31 +00:00
ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
ad_cpu_interconnect 0x44A10000 axi_ad9680_core
ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
# gt uses hp3, and 100MHz clock for both DRP and AXI4
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# interconnect (mem/dac)
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk axi_ad9144_dma/m_src_axi
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
daq2: rebase conflicts
2014-10-22 20:39:17 +00:00
daq2: move intrs into ipi
2015-03-12 20:16:55 +00:00
# interrupts
daq2: rebase conflicts
2014-10-22 20:39:17 +00:00
daq2 : Integrate the DACFIFO into the supported projects. + All pack/unpack logic is made by the cpack and upack modules. + The DAC FIFO is integrated between the TX DMA and cpack. + All the top files are updated, all the projects compiled successfully.
2015-05-11 09:17:59 +00:00
ad_cpu_interrupt ps-12 mb-13 axi_ad9144_dma/irq
ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
daq2: rebase conflicts
2014-10-22 20:39:17 +00:00
daq2/zc706: open ports
2015-06-10 18:25:58 +00:00
ad_connect axi_ad9144_core/dac_ddata_2 GND
ad_connect axi_ad9144_core/dac_ddata_3 GND
dacfifo- bypass port name change
2017-02-27 20:57:53 +00:00
ad_connect axi_ad9144_fifo/bypass GND
daq2/zc706: open ports
2015-06-10 18:25:58 +00:00