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pluto_hdl_adi/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl

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axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
# ip
axi_dacfifo: Move IP to library/xilinx
2016-09-15 08:38:16 +00:00
source ../../scripts/adi_env.tcl
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_dacfifo
adi_ip_files axi_dacfifo [list \
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
library/axi_dacfifo: Update the bypass logic The bypass logic is located between the AXI read controller and the DAC CDC fifo. When the bypass is enabled the DMAC destination interface must be clocked with the PL_DDR controller's ui_clk. This way it can easily switch between the AXI read's stream and DMAC's stream interface.
2016-06-22 09:24:54 +00:00
"$ad_hdl_dir/library/util_axis_resize/util_axis_resize.v" \
"axi_dacfifo_constr.xdc" \
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
"axi_dacfifo_dac.v" \
"axi_dacfifo_wr.v" \
"axi_dacfifo_rd.v" \
library/axi_dacfifo: Update the bypass logic The bypass logic is located between the AXI read controller and the DAC CDC fifo. When the bypass is enabled the DMAC destination interface must be clocked with the PL_DDR controller's ui_clk. This way it can easily switch between the AXI read's stream and DMAC's stream interface.
2016-06-22 09:24:54 +00:00
"axi_dacfifo.v"]
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
adi_ip_properties_lite axi_dacfifo
adi_ip_constraints axi_dacfifo [list \
"axi_dacfifo_constr.xdc" ]
ipx::infer_bus_interfaces {{xilinx.com:interface:aximm:1.0}} [ipx::current_core]
ipx::save_core [ipx::current_core]