pluto_hdl_adi/projects/common/zcu102/zcu102_system_bd.tcl

# create board design
# default ports

create_bd_port -dir O -from 2 -to 0 spi0_csn
create_bd_port -dir O spi0_sclk
create_bd_port -dir O spi0_mosi
create_bd_port -dir I spi0_miso

create_bd_port -dir O -from 2 -to 0 spi1_csn
create_bd_port -dir O spi1_sclk
create_bd_port -dir O spi1_mosi
create_bd_port -dir I spi1_miso

create_bd_port -dir I -from 94 -to 0 gpio_i
create_bd_port -dir O -from 94 -to 0 gpio_o

# interrupts

create_bd_port -dir I -type intr ps_intr_00
create_bd_port -dir I -type intr ps_intr_01
create_bd_port -dir I -type intr ps_intr_02
create_bd_port -dir I -type intr ps_intr_03
create_bd_port -dir I -type intr ps_intr_04
create_bd_port -dir I -type intr ps_intr_05
create_bd_port -dir I -type intr ps_intr_06
create_bd_port -dir I -type intr ps_intr_07
create_bd_port -dir I -type intr ps_intr_08
create_bd_port -dir I -type intr ps_intr_09
create_bd_port -dir I -type intr ps_intr_10
create_bd_port -dir I -type intr ps_intr_11
create_bd_port -dir I -type intr ps_intr_12
create_bd_port -dir I -type intr ps_intr_13
create_bd_port -dir I -type intr ps_intr_14
create_bd_port -dir I -type intr ps_intr_15

# instance: sys_ps8

ad_ip_instance zynq_ultra_ps_e sys_ps8

# defaults -- remove after board is supported in the tool

set_property -dict [list \
  CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS33} \
  CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS33} \
  CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS33} \
  CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \
  CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x80000000} \
  CONFIG.PSU_MIO_0_DIRECTION {out} \
  CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_0_SLEW {slow} \
  CONFIG.PSU_MIO_10_DIRECTION {inout} \
  CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_10_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_10_SLEW {slow} \
  CONFIG.PSU_MIO_11_DIRECTION {inout} \
  CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_11_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_11_SLEW {slow} \
  CONFIG.PSU_MIO_12_DIRECTION {out} \
  CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_12_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_12_SLEW {slow} \
  CONFIG.PSU_MIO_13_DIRECTION {inout} \
  CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_13_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_13_SLEW {slow} \
  CONFIG.PSU_MIO_14_DIRECTION {inout} \
  CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_14_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_14_SLEW {slow} \
  CONFIG.PSU_MIO_15_DIRECTION {inout} \
  CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_15_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_15_SLEW {slow} \
  CONFIG.PSU_MIO_16_DIRECTION {inout} \
  CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_16_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_16_SLEW {slow} \
  CONFIG.PSU_MIO_17_DIRECTION {inout} \
  CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_17_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_17_SLEW {slow} \
  CONFIG.PSU_MIO_18_DIRECTION {in} \
  CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_18_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_18_SLEW {slow} \
  CONFIG.PSU_MIO_19_DIRECTION {out} \
  CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_19_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_19_SLEW {slow} \
  CONFIG.PSU_MIO_1_DIRECTION {inout} \
  CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_1_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_1_SLEW {slow} \
  CONFIG.PSU_MIO_20_DIRECTION {out} \
  CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_20_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_20_SLEW {slow} \
  CONFIG.PSU_MIO_21_DIRECTION {in} \
  CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_21_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_21_SLEW {slow} \
  CONFIG.PSU_MIO_22_DIRECTION {inout} \
  CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_22_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_22_SLEW {slow} \
  CONFIG.PSU_MIO_23_DIRECTION {inout} \
  CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_23_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_23_SLEW {slow} \
  CONFIG.PSU_MIO_24_DIRECTION {out} \
  CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_24_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_24_SLEW {slow} \
  CONFIG.PSU_MIO_25_DIRECTION {in} \
  CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_25_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_25_SLEW {slow} \
  CONFIG.PSU_MIO_26_DIRECTION {inout} \
  CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_26_SLEW {slow} \
  CONFIG.PSU_MIO_27_DIRECTION {inout} \
  CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_27_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_27_SLEW {slow} \
  CONFIG.PSU_MIO_28_DIRECTION {inout} \
  CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_28_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_28_SLEW {slow} \
  CONFIG.PSU_MIO_29_DIRECTION {inout} \
  CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_29_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_29_SLEW {slow} \
  CONFIG.PSU_MIO_2_DIRECTION {inout} \
  CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_2_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_2_SLEW {slow} \
  CONFIG.PSU_MIO_30_DIRECTION {inout} \
  CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_30_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_30_SLEW {slow} \
  CONFIG.PSU_MIO_31_DIRECTION {out} \
  CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_31_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_31_SLEW {slow} \
  CONFIG.PSU_MIO_32_DIRECTION {inout} \
  CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_32_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_32_SLEW {slow} \
  CONFIG.PSU_MIO_33_DIRECTION {inout} \
  CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_33_SLEW {slow} \
  CONFIG.PSU_MIO_34_DIRECTION {inout} \
  CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_34_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_34_SLEW {slow} \
  CONFIG.PSU_MIO_35_DIRECTION {inout} \
  CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_35_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_35_SLEW {slow} \
  CONFIG.PSU_MIO_36_DIRECTION {inout} \
  CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_36_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_36_SLEW {slow} \
  CONFIG.PSU_MIO_37_DIRECTION {inout} \
  CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_37_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_37_SLEW {slow} \
  CONFIG.PSU_MIO_38_DIRECTION {inout} \
  CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_38_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_38_SLEW {slow} \
  CONFIG.PSU_MIO_39_DIRECTION {inout} \
  CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_39_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_39_SLEW {slow} \
  CONFIG.PSU_MIO_3_DIRECTION {inout} \
  CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_3_SLEW {slow} \
  CONFIG.PSU_MIO_40_DIRECTION {inout} \
  CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_40_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_40_SLEW {slow} \
  CONFIG.PSU_MIO_41_DIRECTION {inout} \
  CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_41_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_41_SLEW {slow} \
  CONFIG.PSU_MIO_42_DIRECTION {inout} \
  CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_42_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_42_SLEW {slow} \
  CONFIG.PSU_MIO_43_DIRECTION {out} \
  CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_43_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_43_SLEW {slow} \
  CONFIG.PSU_MIO_44_DIRECTION {in} \
  CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_44_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_44_SLEW {slow} \
  CONFIG.PSU_MIO_45_DIRECTION {in} \
  CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_45_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_45_SLEW {slow} \
  CONFIG.PSU_MIO_46_DIRECTION {inout} \
  CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_46_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_46_SLEW {slow} \
  CONFIG.PSU_MIO_47_DIRECTION {inout} \
  CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_47_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_47_SLEW {slow} \
  CONFIG.PSU_MIO_48_DIRECTION {inout} \
  CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_48_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_48_SLEW {slow} \
  CONFIG.PSU_MIO_49_DIRECTION {inout} \
  CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_49_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_49_SLEW {slow} \
  CONFIG.PSU_MIO_4_DIRECTION {inout} \
  CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_4_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_4_SLEW {slow} \
  CONFIG.PSU_MIO_50_DIRECTION {inout} \
  CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_50_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_50_SLEW {slow} \
  CONFIG.PSU_MIO_51_DIRECTION {out} \
  CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_51_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_51_SLEW {slow} \
  CONFIG.PSU_MIO_52_DIRECTION {in} \
  CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_52_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_52_SLEW {slow} \
  CONFIG.PSU_MIO_53_DIRECTION {in} \
  CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_53_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_53_SLEW {slow} \
  CONFIG.PSU_MIO_54_DIRECTION {inout} \
  CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_54_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_54_SLEW {slow} \
  CONFIG.PSU_MIO_55_DIRECTION {in} \
  CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_55_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_55_SLEW {slow} \
  CONFIG.PSU_MIO_56_DIRECTION {inout} \
  CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_56_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_56_SLEW {slow} \
  CONFIG.PSU_MIO_57_DIRECTION {inout} \
  CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_57_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_57_SLEW {slow} \
  CONFIG.PSU_MIO_58_DIRECTION {out} \
  CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_58_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_58_SLEW {slow} \
  CONFIG.PSU_MIO_59_DIRECTION {inout} \
  CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_59_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_59_SLEW {slow} \
  CONFIG.PSU_MIO_5_DIRECTION {out} \
  CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_5_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_5_SLEW {slow} \
  CONFIG.PSU_MIO_60_DIRECTION {inout} \
  CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_60_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_60_SLEW {slow} \
  CONFIG.PSU_MIO_61_DIRECTION {inout} \
  CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_61_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_61_SLEW {slow} \
  CONFIG.PSU_MIO_62_DIRECTION {inout} \
  CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_62_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_62_SLEW {slow} \
  CONFIG.PSU_MIO_63_DIRECTION {inout} \
  CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_63_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_63_SLEW {slow} \
  CONFIG.PSU_MIO_64_DIRECTION {out} \
  CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_64_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_64_SLEW {slow} \
  CONFIG.PSU_MIO_65_DIRECTION {out} \
  CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_65_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_65_SLEW {slow} \
  CONFIG.PSU_MIO_66_DIRECTION {out} \
  CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_66_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_66_SLEW {slow} \
  CONFIG.PSU_MIO_67_DIRECTION {out} \
  CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_67_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_67_SLEW {slow} \
  CONFIG.PSU_MIO_68_DIRECTION {out} \
  CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_68_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_68_SLEW {slow} \
  CONFIG.PSU_MIO_69_DIRECTION {out} \
  CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_69_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_69_SLEW {slow} \
  CONFIG.PSU_MIO_6_DIRECTION {out} \
  CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_6_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_6_SLEW {slow} \
  CONFIG.PSU_MIO_70_DIRECTION {in} \
  CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_70_SLEW {slow} \
  CONFIG.PSU_MIO_71_DIRECTION {in} \
  CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_71_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_71_SLEW {slow} \
  CONFIG.PSU_MIO_72_DIRECTION {in} \
  CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_72_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_72_SLEW {slow} \
  CONFIG.PSU_MIO_73_DIRECTION {in} \
  CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_73_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_73_SLEW {slow} \
  CONFIG.PSU_MIO_74_DIRECTION {in} \
  CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_74_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_74_SLEW {slow} \
  CONFIG.PSU_MIO_75_DIRECTION {in} \
  CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_75_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_75_SLEW {slow} \
  CONFIG.PSU_MIO_76_DIRECTION {out} \
  CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_76_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_76_SLEW {slow} \
  CONFIG.PSU_MIO_77_DIRECTION {inout} \
  CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_77_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_77_SLEW {slow} \
  CONFIG.PSU_MIO_7_DIRECTION {out} \
  CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_7_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_7_SLEW {slow} \
  CONFIG.PSU_MIO_8_DIRECTION {inout} \
  CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_8_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_8_SLEW {slow} \
  CONFIG.PSU_MIO_9_DIRECTION {inout} \
  CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
  CONFIG.PSU_MIO_9_INPUT_TYPE {schmitt} \
  CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
  CONFIG.PSU_MIO_9_SLEW {slow} \
  CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#PCIE#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
  CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#so_mo1#mo2#mo3#si_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#gpio1[30]#reset_n#gpio1[32]#gpio1[33]#gpio1[34]#gpio1[35]#gpio1[36]#gpio1[37]#gpio1[38]#gpio1[39]#gpio1[40]#gpio1[41]#gpio1[42]#sdio1_bus_pow#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \
  CONFIG.PSU_PACKAGE_DDR_BOARD_DELAY3 {0.100} \
  CONFIG.PSU_PRESET_BANK0_VOLTAGE {<Select>} \
  CONFIG.PSU_PRESET_BANK1_VOLTAGE {<Select>} \
  CONFIG.PSU_UIPARAM_GENERATE_SUMMARY {<Select>} \
  CONFIG.PSU__ACPU0__POWER__ON {1} \
  CONFIG.PSU__ACPU1__POWER__ON {1} \
  CONFIG.PSU__ACPU2__POWER__ON {1} \
  CONFIG.PSU__ACPU3__POWER__ON {1} \
  CONFIG.PSU__ACT_DDR_FREQ_MHZ {1} \
  CONFIG.PSU__ADMA_COHERENCY {1} \
  CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
  CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
  CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \
  CONFIG.PSU__CAN0__GRP_CLK__IO {<Select>} \
  CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__CAN0__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
  CONFIG.PSU__CAN1__GRP_CLK__IO {<Select>} \
  CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
  CONFIG.PSU__CPU_CPU_6X4X_MAX_RANGE {1} \
  CONFIG.PSU__CPU_R5__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1099.989014} \
  CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
  CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
  CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
  CONFIG.PSU__CRF_APB__ACPU__ENABLE {1} \
  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
  CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
  CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
  CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
  CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
  CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
  CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
  CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
  CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {66} \
  CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000} \
  CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
  CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
  CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
  CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
  CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__SRCSEL {APLL} \
  CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
  CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
  CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
  CONFIG.PSU__CRF_APB__APM_CTRL__SRCSEL {<Select>} \
  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \
  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRF_APB__DBG_FPD__ENABLE {1} \
  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {249.997498} \
  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRF_APB__DBG_TRACE__ENABLE {1} \
  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \
  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRF_APB__DBG_TSTMP__ENABLE {1} \
  CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {533.328003} \
  CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
  CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
  CONFIG.PSU__CRF_APB__DFT125_REF_CTRL__DIVISOR0 {10} \
  CONFIG.PSU__CRF_APB__DFT125_REF_CTRL__SRCSEL {APLL} \
  CONFIG.PSU__CRF_APB__DFT250_REF_CTRL__DIVISOR0 {5} \
  CONFIG.PSU__CRF_APB__DFT250_REF_CTRL__SRCSEL {APLL} \
  CONFIG.PSU__CRF_APB__DFT270_REF_CTRL__DIVISOR0 {5} \
  CONFIG.PSU__CRF_APB__DFT270_REF_CTRL__SRCSEL {APLL} \
  CONFIG.PSU__CRF_APB__DFT300_REF_CTRL__DIVISOR0 {4} \
  CONFIG.PSU__CRF_APB__DFT300_REF_CTRL__SRCSEL {DPLL} \
  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {549.994507} \
  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
  CONFIG.PSU__CRF_APB__DPDMA__ENABLE {1} \
  CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
  CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
  CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000} \
  CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
  CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
  CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
  CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
  CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__SRCSEL {DPLL} \
  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000} \
  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {39} \
  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {VPLL} \
  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {27.000} \
  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {17} \
  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {269.997} \
  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {3} \
  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {320} \
  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {RPLL} \
  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {549.994507} \
  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
  CONFIG.PSU__CRF_APB__GDMA__ENABLE {1} \
  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {499.994995} \
  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRF_APB__GPU__ENABLE {1} \
  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {124.998749} \
  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {4} \
  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {125} \
  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {1} \
  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {249.997498} \
  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.997498} \
  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.998999} \
  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRF_APB__TOPSW_LSBUS__ENABLE {1} \
  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {479.228546} \
  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {VPLL} \
  CONFIG.PSU__CRF_APB__TOPSW_MAIN__ENABLE {1} \
  CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
  CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {57} \
  CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.508} \
  CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
  CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
  CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
  CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
  CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__SRCSEL {VPLL} \
  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \
  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__ADMA__ENABLE {1} \
  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {499.995} \
  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {2} \
  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000} \
  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {20} \
  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__AMS__ENABLE {0} \
  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {99.999} \
  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {99.998999} \
  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \
  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {399.996012} \
  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {500} \
  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {RPLL} \
  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \
  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__DBG_LPD__ENABLE {1} \
  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
  CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500} \
  CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
  CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {124.999} \
  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {124.999} \
  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {124.999} \
  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \
  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {216.664} \
  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {3} \
  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {RPLL} \
  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.998999} \
  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.998999} \
  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
  CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
  CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000} \
  CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
  CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
  CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
  CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
  CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \
  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {267} \
  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__IOU_SWITCH__ENABLE {1} \
  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.998999} \
  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__LPD_LSBUS__ENABLE {1} \
  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \
  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__LPD_SWITCH__ENABLE {1} \
  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {99.999} \
  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__OCM_MAIN__ENABLE {1} \
  CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {199.998006} \
  CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {6} \
  CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {250} \
  CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {RPLL} \
  CONFIG.PSU__CRL_APB__PCAP__ENABLE {1} \
  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__ACT_FREQMHZ {1300} \
  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__DIVISOR0 {32} \
  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__FREQMHZ {1300} \
  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__ACT_FREQMHZ {1300} \
  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__DIVISOR0 {1} \
  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__FREQMHZ {1300} \
  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__ACT_FREQMHZ {300} \
  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__DIVISOR0 {1} \
  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__FREQMHZ {300} \
  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.998999} \
  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \
  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {324.997} \
  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {400} \
  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {324.997} \
  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {400} \
  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {324.997} \
  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {400} \
  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \
  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {300} \
  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
  CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {72} \
  CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000} \
  CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
  CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
  CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
  CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
  CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__SRCSEL {RPLL} \
  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {185.712} \
  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {6} \
  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {199.998006} \
  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {6} \
  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {RPLL} \
  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {185.712} \
  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {6} \
  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {185.712} \
  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {6} \
  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.998999} \
  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__TIMESTAMP__ENABLE {1} \
  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.998999} \
  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.998999} \
  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \
  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {249.997} \
  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \
  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
  CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
  CONFIG.PSU__CRYSTAL__PERIPHERAL__FREQMHZ {33.333} \
  CONFIG.PSU__CSU_COHERENCY {1} \
  CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_0__RESPONSE {<Select>} \
  CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_10__RESPONSE {<Select>} \
  CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_11__RESPONSE {<Select>} \
  CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_12__RESPONSE {<Select>} \
  CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_1__RESPONSE {<Select>} \
  CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_2__RESPONSE {<Select>} \
  CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_3__RESPONSE {<Select>} \
  CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_4__RESPONSE {<Select>} \
  CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_5__RESPONSE {<Select>} \
  CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_6__RESPONSE {<Select>} \
  CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_7__RESPONSE {<Select>} \
  CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_8__RESPONSE {<Select>} \
  CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \
  CONFIG.PSU__CSU__CSU_TAMPER_9__RESPONSE {<Select>} \
  CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__CSU__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__DAP_COHERENCY {1} \
  CONFIG.PSU__DDRC__ADDR_MIRROR {NA} \
  CONFIG.PSU__DDRC__AL {0} \
  CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
  CONFIG.PSU__DDRC__BG_ADDR_COUNT {2} \
  CONFIG.PSU__DDRC__BL {8} \
  CONFIG.PSU__DDRC__BOARD_DELAY0 {1} \
  CONFIG.PSU__DDRC__BOARD_DELAY1 {1} \
  CONFIG.PSU__DDRC__BOARD_DELAY2 {1} \
  CONFIG.PSU__DDRC__BOARD_DELAY3 {1} \
  CONFIG.PSU__DDRC__BRC_MAPPING {0} \
  CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
  CONFIG.PSU__DDRC__CL {15} \
  CONFIG.PSU__DDRC__CLOCK_0_LENGTH_MM {1} \
  CONFIG.PSU__DDRC__CLOCK_0_PACKAGE_LENGTH {1} \
  CONFIG.PSU__DDRC__CLOCK_0_PROPOGATION_DELAY {1} \
  CONFIG.PSU__DDRC__CLOCK_1_LENGTH_MM {1} \
  CONFIG.PSU__DDRC__CLOCK_1_PACKAGE_LENGTH {1} \
  CONFIG.PSU__DDRC__CLOCK_1_PROPOGATION_DELAY {1} \
  CONFIG.PSU__DDRC__CLOCK_2_LENGTH_MM {1} \
  CONFIG.PSU__DDRC__CLOCK_2_PACKAGE_LENGTH {1} \
  CONFIG.PSU__DDRC__CLOCK_2_PROPOGATION_DELAY {1} \
  CONFIG.PSU__DDRC__CLOCK_3_LENGTH_MM {1} \
  CONFIG.PSU__DDRC__CLOCK_3_PACKAGE_LENGTH {1} \
  CONFIG.PSU__DDRC__CLOCK_3_PROPOGATION_DELAY {1} \
  CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
  CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
  CONFIG.PSU__DDRC__CWL {14} \
  CONFIG.PSU__DDRC__DATA_MASK {1} \
  CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
  CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
  CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
  CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
  CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
  CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {0} \
  CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
  CONFIG.PSU__DDRC__DERATE_INT_D {<Select>} \
  CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
  CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
  CONFIG.PSU__DDRC__DQS_0_LENGTH_MM {1} \
  CONFIG.PSU__DDRC__DQS_0_PACKAGE_LENGTH {1} \
  CONFIG.PSU__DDRC__DQS_0_PROPOGATION_DELAY {1} \
  CONFIG.PSU__DDRC__DQS_1_LENGTH_MM {1} \
  CONFIG.PSU__DDRC__DQS_1_PACKAGE_LENGTH {1} \
  CONFIG.PSU__DDRC__DQS_1_PROPOGATION_DELAY {1} \
  CONFIG.PSU__DDRC__DQS_2_LENGTH_MM {1} \
  CONFIG.PSU__DDRC__DQS_2_PACKAGE_LENGTH {1} \
  CONFIG.PSU__DDRC__DQS_2_PROPOGATION_DELAY {1} \
  CONFIG.PSU__DDRC__DQS_3_LENGTH_MM {1} \
  CONFIG.PSU__DDRC__DQS_3_PACKAGE_LENGTH {1} \
  CONFIG.PSU__DDRC__DQS_3_PROPOGATION_DELAY {1} \
  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_0 {0.00} \
  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_1 {0.05} \
  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_2 {0.10} \
  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_3 {0.15} \
  CONFIG.PSU__DDRC__DQ_0_LENGTH_MM {1} \
  CONFIG.PSU__DDRC__DQ_0_PACKAGE_LENGTH {1} \
  CONFIG.PSU__DDRC__DQ_0_PROPOGATION_DELAY {1} \
  CONFIG.PSU__DDRC__DQ_1_LENGTH_MM {1} \
  CONFIG.PSU__DDRC__DQ_1_PACKAGE_LENGTH {1} \
  CONFIG.PSU__DDRC__DQ_1_PROPOGATION_DELAY {1} \
  CONFIG.PSU__DDRC__DQ_2_LENGTH_MM {1} \
  CONFIG.PSU__DDRC__DQ_2_PACKAGE_LENGTH {1} \
  CONFIG.PSU__DDRC__DQ_2_PROPOGATION_DELAY {1} \
  CONFIG.PSU__DDRC__DQ_3_LENGTH_MM {1} \
  CONFIG.PSU__DDRC__DQ_3_PACKAGE_LENGTH {1} \
  CONFIG.PSU__DDRC__DQ_3_PROPOGATION_DELAY {1} \
  CONFIG.PSU__DDRC__DRAM_WIDTH {8 Bits} \
  CONFIG.PSU__DDRC__ECC {0} \
  CONFIG.PSU__DDRC__ECC_SCRUB {0} \
  CONFIG.PSU__DDRC__ENABLE {1} \
  CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
  CONFIG.PSU__DDRC__FGRM {0} \
  CONFIG.PSU__DDRC__FREQ_MHZ {1066.50} \
  CONFIG.PSU__DDRC__HIGH_TEMP {<Select>} \
  CONFIG.PSU__DDRC__LP_ASR {0} \
  CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
  CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
  CONFIG.PSU__DDRC__PARTNO {<Select>} \
  CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
  CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
  CONFIG.PSU__DDRC__PLL_BYPASS {0} \
  CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
  CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
  CONFIG.PSU__DDRC__RDIMM_INDICATOR {0} \
  CONFIG.PSU__DDRC__RD_DBI_ENABLE {0} \
  CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
  CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
  CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
  CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
  CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
  CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
  CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
  CONFIG.PSU__DDRC__T_FAW {21.0} \
  CONFIG.PSU__DDRC__T_RAS_MIN {33} \
  CONFIG.PSU__DDRC__T_RC {46.5} \
  CONFIG.PSU__DDRC__T_RCD {15} \
  CONFIG.PSU__DDRC__T_RP {15} \
  CONFIG.PSU__DDRC__UDIMM_INDICATOR {1} \
  CONFIG.PSU__DDRC__USE_INTERNAL_VREF {0} \
  CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
  CONFIG.PSU__DDRC__VREF {1} \
  CONFIG.PSU__DDRC__WR_DBI_ENABLE {0} \
  CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \
  CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
  CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {<Select>} \
  CONFIG.PSU__DISPLAYPORT__LANE0__IO {<Select>} \
  CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {<Select>} \
  CONFIG.PSU__DISPLAYPORT__LANE1__IO {<Select>} \
  CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__DPAUX__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__DP__LANE_SEL {<Select>} \
  CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \
  CONFIG.PSU__ENET0__GRP_MDIO__IO {<Select>} \
  CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__ENET0__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \
  CONFIG.PSU__ENET1__GRP_MDIO__IO {<Select>} \
  CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__ENET1__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \
  CONFIG.PSU__ENET2__GRP_MDIO__IO {<Select>} \
  CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__ENET2__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
  CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
  CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
  CONFIG.PSU__FPGA_PL0_ENABLE {1} \
  CONFIG.PSU__FP__POWER__ON {1} \
  CONFIG.PSU__GEM0_COHERENCY {1} \
  CONFIG.PSU__GEM1_COHERENCY {0} \
  CONFIG.PSU__GEM2_COHERENCY {1} \
  CONFIG.PSU__GEM3_COHERENCY {1} \
  CONFIG.PSU__GEM__TSU__ENABLE {0} \
  CONFIG.PSU__GEM__TSU__IO {<Select>} \
  CONFIG.PSU__GENERATE_SECURITY_REGISTERS {0} \
  CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
  CONFIG.PSU__GEN_IPI_10__MASTER {S_AXI_LPD} \
  CONFIG.PSU__GEN_IPI_1__MASTER {RPU} \
  CONFIG.PSU__GEN_IPI_2__MASTER {RPU} \
  CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
  CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
  CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
  CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
  CONFIG.PSU__GEN_IPI_7__MASTER {S_AXI_HP1_FPD} \
  CONFIG.PSU__GEN_IPI_8__MASTER {S_AXI_HP2_FPD} \
  CONFIG.PSU__GEN_IPI_9__MASTER {S_AXI_HP3_FPD} \
  CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
  CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
  CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__GPIO2_MIO__IO {<Select>} \
  CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
  CONFIG.PSU__GPU_PP0__POWER__ON {1} \
  CONFIG.PSU__GPU_PP1__POWER__ON {1} \
  CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
  CONFIG.PSU__GT__LANE0_REF_SEL {Ref Clk0} \
  CONFIG.PSU__GT__LANE1_REF_SEL {Ref Clk0} \
  CONFIG.PSU__GT__LANE2_REF_SEL {Ref Clk2} \
  CONFIG.PSU__GT__LANE3_REF_SEL {Ref Clk1} \
  CONFIG.PSU__GT__LINK_SPEED {<Select>} \
  CONFIG.PSU__GT__REF_SEL0 {100} \
  CONFIG.PSU__GT__REF_SEL1 {100} \
  CONFIG.PSU__GT__REF_SEL2 {26} \
  CONFIG.PSU__GT__REF_SEL3 {125} \
  CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
  CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
  CONFIG.PSU__I2C0__GRP_INT__IO {<Select>} \
  CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \
  CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
  CONFIG.PSU__I2C1__GRP_INT__IO {<Select>} \
  CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
  CONFIG.PSU__L2_BANK0__POWER__ON {1} \
  CONFIG.PSU__MAXIGP2__DATA_WIDTH {64} \
  CONFIG.PSU__NAND_COHERENCY {1} \
  CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \
  CONFIG.PSU__NAND__CHIP_ENABLE__IO {<Select>} \
  CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \
  CONFIG.PSU__NAND__DATA_STROBE__IO {<Select>} \
  CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__NAND__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
  CONFIG.PSU__NAND__READY_BUSY__IO {<Select>} \
  CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
  CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
  CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
  CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
  CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
  CONFIG.PSU__PCIE__ACS_VIOLATION {0} \
  CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
  CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \
  CONFIG.PSU__PCIE__BAR0_64BIT {0} \
  CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
  CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \
  CONFIG.PSU__PCIE__BAR0_SCALE {<Select>} \
  CONFIG.PSU__PCIE__BAR0_SIZE {<Select>} \
  CONFIG.PSU__PCIE__BAR0_TYPE {<Select>} \
  CONFIG.PSU__PCIE__BAR0_VAL {0x0} \
  CONFIG.PSU__PCIE__BAR1_64BIT {0} \
  CONFIG.PSU__PCIE__BAR1_ENABLE {0} \
  CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \
  CONFIG.PSU__PCIE__BAR1_SCALE {<Select>} \
  CONFIG.PSU__PCIE__BAR1_SIZE {<Select>} \
  CONFIG.PSU__PCIE__BAR1_TYPE {<Select>} \
  CONFIG.PSU__PCIE__BAR1_VAL {0x0} \
  CONFIG.PSU__PCIE__BAR2_64BIT {0} \
  CONFIG.PSU__PCIE__BAR2_ENABLE {0} \
  CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \
  CONFIG.PSU__PCIE__BAR2_SCALE {<Select>} \
  CONFIG.PSU__PCIE__BAR2_SIZE {<Select>} \
  CONFIG.PSU__PCIE__BAR2_TYPE {<Select>} \
  CONFIG.PSU__PCIE__BAR2_VAL {0x0} \
  CONFIG.PSU__PCIE__BAR3_64BIT {0} \
  CONFIG.PSU__PCIE__BAR3_ENABLE {0} \
  CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \
  CONFIG.PSU__PCIE__BAR3_SCALE {<Select>} \
  CONFIG.PSU__PCIE__BAR3_SIZE {<Select>} \
  CONFIG.PSU__PCIE__BAR3_TYPE {<Select>} \
  CONFIG.PSU__PCIE__BAR3_VAL {0x0} \
  CONFIG.PSU__PCIE__BAR4_64BIT {0} \
  CONFIG.PSU__PCIE__BAR4_ENABLE {0} \
  CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \
  CONFIG.PSU__PCIE__BAR4_SCALE {<Select>} \
  CONFIG.PSU__PCIE__BAR4_SIZE {<Select>} \
  CONFIG.PSU__PCIE__BAR4_TYPE {<Select>} \
  CONFIG.PSU__PCIE__BAR4_VAL {0x0} \
  CONFIG.PSU__PCIE__BAR5_64BIT {0} \
  CONFIG.PSU__PCIE__BAR5_ENABLE {0} \
  CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \
  CONFIG.PSU__PCIE__BAR5_SCALE {<Select>} \
  CONFIG.PSU__PCIE__BAR5_SIZE {<Select>} \
  CONFIG.PSU__PCIE__BAR5_TYPE {<Select>} \
  CONFIG.PSU__PCIE__BAR5_VAL {0x0} \
  CONFIG.PSU__PCIE__BASE_CLASS_MENU {<Select>} \
  CONFIG.PSU__PCIE__BRIDGE_BAR_INDICATOR {<Select>} \
  CONFIG.PSU__PCIE__CAP_SLOT_IMPLEMENTED {<Select>} \
  CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \
  CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {0x0} \
  CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \
  CONFIG.PSU__PCIE__CLASS_CODE_VALUE {0x60400} \
  CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \
  CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \
  CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \
  CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {1} \
  CONFIG.PSU__PCIE__DEVICE_ID {0xD021} \
  CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {Root Port} \
  CONFIG.PSU__PCIE__ECRC_CHECK {0} \
  CONFIG.PSU__PCIE__ECRC_ERR {0} \
  CONFIG.PSU__PCIE__ECRC_GEN {0} \
  CONFIG.PSU__PCIE__EROM_ENABLE {0} \
  CONFIG.PSU__PCIE__EROM_SCALE {<Select>} \
  CONFIG.PSU__PCIE__EROM_SIZE {<Select>} \
  CONFIG.PSU__PCIE__EROM_VAL {0x0} \
  CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \
  CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \
  CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \
  CONFIG.PSU__PCIE__INTERFACE_WIDTH {<Select>} \
  CONFIG.PSU__PCIE__INTX_GENERATION {0} \
  CONFIG.PSU__PCIE__INTX_PIN {<Select>} \
  CONFIG.PSU__PCIE__LANE0__ENABLE {1} \
  CONFIG.PSU__PCIE__LANE0__IO {GT Lane0} \
  CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
  CONFIG.PSU__PCIE__LANE1__IO {<Select>} \
  CONFIG.PSU__PCIE__LANE2__ENABLE {0} \
  CONFIG.PSU__PCIE__LANE2__IO {<Select>} \
  CONFIG.PSU__PCIE__LANE3__ENABLE {0} \
  CONFIG.PSU__PCIE__LANE3__IO {<Select>} \
  CONFIG.PSU__PCIE__LEGACY_INTERRUPT {<Select>} \
  CONFIG.PSU__PCIE__LINK_SPEED {5.0 Gb/s} \
  CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH {x1} \
  CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE {256 bytes} \
  CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \
  CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {<Select>} \
  CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
  CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {<Select>} \
  CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \
  CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \
  CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \
  CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \
  CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
  CONFIG.PSU__PCIE__MSI_MULTIPLE_MSG_CAPABLE {<Select>} \
  CONFIG.PSU__PCIE__MULTIHEADER {0} \
  CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {0} \
  CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_IO {<Select>} \
  CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {1} \
  CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {MIO 31} \
  CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \
  CONFIG.PSU__PCIE__RECEIVER_ERR {0} \
  CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \
  CONFIG.PSU__PCIE__REVISION_ID {0x0} \
  CONFIG.PSU__PCIE__SUBSYSTEM_ID {0x7} \
  CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {0x10EE} \
  CONFIG.PSU__PCIE__SUB_CLASS_INTERFACE_MENU {<Select>} \
  CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \
  CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \
  CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \
  CONFIG.PSU__PCIE__USE_CLASS_CODE_LOOKUP_ASSISTANT {<Select>} \
  CONFIG.PSU__PCIE__VENDOR_ID {0x10EE} \
  CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__PJTAG__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__PL__POWER__ON {1} \
  CONFIG.PSU__PMU_COHERENCY {1} \
  CONFIG.PSU__PMU__EMIO_GPI__ENABLE {<Select>} \
  CONFIG.PSU__PMU__EMIO_GPO__ENABLE {<Select>} \
  CONFIG.PSU__PMU__GPI0__ENABLE {<Select>} \
  CONFIG.PSU__PMU__GPI0__IO {<Select>} \
  CONFIG.PSU__PMU__GPI1__ENABLE {<Select>} \
  CONFIG.PSU__PMU__GPI1__IO {<Select>} \
  CONFIG.PSU__PMU__GPI2__ENABLE {<Select>} \
  CONFIG.PSU__PMU__GPI2__IO {<Select>} \
  CONFIG.PSU__PMU__GPI3__ENABLE {<Select>} \
  CONFIG.PSU__PMU__GPI3__IO {<Select>} \
  CONFIG.PSU__PMU__GPI4__ENABLE {<Select>} \
  CONFIG.PSU__PMU__GPI4__IO {<Select>} \
  CONFIG.PSU__PMU__GPI5__ENABLE {<Select>} \
  CONFIG.PSU__PMU__GPI5__IO {<Select>} \
  CONFIG.PSU__PMU__GPO0__ENABLE {<Select>} \
  CONFIG.PSU__PMU__GPO0__IO {<Select>} \
  CONFIG.PSU__PMU__GPO1__ENABLE {<Select>} \
  CONFIG.PSU__PMU__GPO1__IO {<Select>} \
  CONFIG.PSU__PMU__GPO2__ENABLE {<Select>} \
  CONFIG.PSU__PMU__GPO2__IO {<Select>} \
  CONFIG.PSU__PMU__GPO3__ENABLE {<Select>} \
  CONFIG.PSU__PMU__GPO3__IO {<Select>} \
  CONFIG.PSU__PMU__GPO4__ENABLE {<Select>} \
  CONFIG.PSU__PMU__GPO4__IO {<Select>} \
  CONFIG.PSU__PMU__GPO5__ENABLE {<Select>} \
  CONFIG.PSU__PMU__GPO5__IO {<Select>} \
  CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__PMU__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__ANALOG {0.004} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__DDR {0.711} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__FPD {1.163} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__LPD {0.288} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__MIO {0.161} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__PLL {0.067} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__SERDES {0.160} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__TOTAL {2.554} \
  CONFIG.PSU__POWER_SUMMARY__ONCHIP {4.001} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__ANALOG {0.034} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__DDR {0.000} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__FPD {1.785} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__LPD {0.366} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__MIO {0.000} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__PLL {0.003} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__SERDES {0.000} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__TOTAL {1.447} \
  CONFIG.PSU__POWER__ACPU__VCCPSINTFP {0.440} \
  CONFIG.PSU__POWER__AFI_FPD__VCCPSINTFP {0.113} \
  CONFIG.PSU__POWER__AFI_LPD__VCCPSINTLP {0.028} \
  CONFIG.PSU__POWER__APLL__VCCPSPLL {0.016} \
  CONFIG.PSU__POWER__CAN0__VCCPSIO {0} \
  CONFIG.PSU__POWER__CAN1__VCCPSIO {0.004} \
  CONFIG.PSU__POWER__CSU__VCCPSIO {0} \
  CONFIG.PSU__POWER__DDR__VCCPSDDR {0.711} \
  CONFIG.PSU__POWER__DDR__VCCPSINTFP {0} \
  CONFIG.PSU__POWER__DPAUX__VCCPSIO {0} \
  CONFIG.PSU__POWER__DPLL__VCCPSPLL {0} \
  CONFIG.PSU__POWER__DP__VCCPSGTA {0.000} \
  CONFIG.PSU__POWER__DP__VCCPSINTFP {0.000} \
  CONFIG.PSU__POWER__FPINT__VCCPSINTFP {0.232} \
  CONFIG.PSU__POWER__GEM0__VCCPSINTLP {0.000} \
  CONFIG.PSU__POWER__GEM0__VCCPSIO {0} \
  CONFIG.PSU__POWER__GEM1__VCCPSINTLP {0.000} \
  CONFIG.PSU__POWER__GEM1__VCCPSIO {0} \
  CONFIG.PSU__POWER__GEM2__VCCPSINTLP {0.000} \
  CONFIG.PSU__POWER__GEM2__VCCPSIO {0} \
  CONFIG.PSU__POWER__GEM3__VCCPSINTLP {0.006} \
  CONFIG.PSU__POWER__GEM3__VCCPSIO {0.034} \
  CONFIG.PSU__POWER__GPIO0__VCCPSIO {0} \
  CONFIG.PSU__POWER__GPIO1__VCCPSIO {0} \
  CONFIG.PSU__POWER__GPIO2__VCCPSIO {0} \
  CONFIG.PSU__POWER__GPU__VCCPSINTFP {0.318} \
  CONFIG.PSU__POWER__IOPLL__VCCPSPLL {0.018} \
  CONFIG.PSU__POWER__LPINT__VCCPSINTLP {0.115} \
  CONFIG.PSU__POWER__NAND__VCCPSINTLP {0.000} \
  CONFIG.PSU__POWER__NAND__VCCPSIO {0} \
  CONFIG.PSU__POWER__PCIE__VCCPSGTA {0.043} \
  CONFIG.PSU__POWER__PCIE__VCCPSINTFP {0.014} \
  CONFIG.PSU__POWER__PJTAG__VCCPSIO {0} \
  CONFIG.PSU__POWER__PMU__VCCPSIO {0} \
  CONFIG.PSU__POWER__QSPI__VCCPSINTLP {0.002} \
  CONFIG.PSU__POWER__QSPI__VCCPSIO {0.018} \
  CONFIG.PSU__POWER__RPLL__VCCPSPLL {0.016} \
  CONFIG.PSU__POWER__RPU__VCCPSINTLP {0.109} \
  CONFIG.PSU__POWER__SATA__VCCPSGTA {0.060} \
  CONFIG.PSU__POWER__SATA__VCCPSINTFP {0.005} \
  CONFIG.PSU__POWER__SD0__VCCPSIO {0} \
  CONFIG.PSU__POWER__SD1__VCCPSIO {0.047} \
  CONFIG.PSU__POWER__SGMII__VCCPSGTA {0.000} \
  CONFIG.PSU__POWER__SPI0__VCCPSIO {0} \
  CONFIG.PSU__POWER__SPI1__VCCPSIO {0} \
  CONFIG.PSU__POWER__TRACE__VCCPSIO {0} \
  CONFIG.PSU__POWER__TTC0__VCCPSIO {0} \
  CONFIG.PSU__POWER__TTC1__VCCPSIO {0} \
  CONFIG.PSU__POWER__TTC2__VCCPSIO {0} \
  CONFIG.PSU__POWER__TTC3__VCCPSIO {0} \
  CONFIG.PSU__POWER__UART0__VCCPSIO {0.004} \
  CONFIG.PSU__POWER__UART1__VCCPSIO {0.004} \
  CONFIG.PSU__POWER__USB0__VCCPSINTLP {0.017} \
  CONFIG.PSU__POWER__USB0__VCCPSIO {0.046} \
  CONFIG.PSU__POWER__USB1__VCCPSINTLP {0.000} \
  CONFIG.PSU__POWER__USB1__VCCPSIO {0} \
  CONFIG.PSU__POWER__USB3__VCCPSGTA {0.057} \
  CONFIG.PSU__POWER__VPLL__VCCPSPLL {0.017} \
  CONFIG.PSU__POWER__WDT0__VCCPSIO {0} \
  CONFIG.PSU__POWER__WDT1__VCCPSIO {0} \
  CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
  CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \
  CONFIG.PSU__QSPI_COHERENCY {1} \
  CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
  CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
  CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
  CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \
  CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \
  CONFIG.PSU__RPU_COHERENCY {0} \
  CONFIG.PSU__RPU__POWER__ON {1} \
  CONFIG.PSU__SATA__LANE0__ENABLE {0} \
  CONFIG.PSU__SATA__LANE0__IO {<Select>} \
  CONFIG.PSU__SATA__LANE1__ENABLE {1} \
  CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
  CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__SD0_COHERENCY {1} \
  CONFIG.PSU__SD0__DATA_TRANSFER_MODE {<Select>} \
  CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \
  CONFIG.PSU__SD0__GRP_CD__IO {<Select>} \
  CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
  CONFIG.PSU__SD0__GRP_POW__IO {<Select>} \
  CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
  CONFIG.PSU__SD0__GRP_WP__IO {<Select>} \
  CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__SD0__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__SD0__RESET__ENABLE {0} \
  CONFIG.PSU__SD0__SLOT_TYPE {<Select>} \
  CONFIG.PSU__SD1_COHERENCY {1} \
  CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
  CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
  CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
  CONFIG.PSU__SD1__GRP_POW__ENABLE {1} \
  CONFIG.PSU__SD1__GRP_POW__IO {MIO 43} \
  CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \
  CONFIG.PSU__SD1__GRP_WP__IO {MIO 44} \
  CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
  CONFIG.PSU__SD1__RESET__ENABLE {<Select>} \
  CONFIG.PSU__SD1__SLOT_TYPE {SD} \
  CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
  CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \
  CONFIG.PSU__SPI0__GRP_SS0__IO {<Select>} \
  CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
  CONFIG.PSU__SPI0__GRP_SS1__IO {<Select>} \
  CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
  CONFIG.PSU__SPI0__GRP_SS2__IO {<Select>} \
  CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__SPI0__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \
  CONFIG.PSU__SPI1__GRP_SS0__IO {<Select>} \
  CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
  CONFIG.PSU__SPI1__GRP_SS1__IO {<Select>} \
  CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
  CONFIG.PSU__SPI1__GRP_SS2__IO {<Select>} \
  CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__SPI1__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__SWDT0__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__SWDT1__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__TCM0A__POWER__ON {1} \
  CONFIG.PSU__TCM0B__POWER__ON {1} \
  CONFIG.PSU__TCM1A__POWER__ON {1} \
  CONFIG.PSU__TCM1B__POWER__ON {1} \
  CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__TRACE__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__TRACE__WIDTH {<Select>} \
  CONFIG.PSU__TRISTATE__INVERTED {0} \
  CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__TTC0__PERIPHERAL__IO {EMIO} \
  CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__TTC1__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__TTC2__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__TTC3__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
  CONFIG.PSU__UART0__BAUD_RATE {115200} \
  CONFIG.PSU__UART0__MODEM__ENABLE {0} \
  CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
  CONFIG.PSU__UART1__BAUD_RATE {115200} \
  CONFIG.PSU__UART1__MODEM__ENABLE {0} \
  CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
  CONFIG.PSU__USB0_COHERENCY {1} \
  CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
  CONFIG.PSU__USB1_COHERENCY {1} \
  CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__USB1__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
  CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \
  CONFIG.PSU__USB3_1__PERIPHERAL__IO {<Select>} \
  CONFIG.PSU__USE__FABRIC__RST {1} \
  CONFIG.PSU__USE__IRQ0 {1} \
  CONFIG.PSU__USE__M_AXI_GP2 {1} \
  CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
] [get_bd_cells sys_ps8]

set_property -dict [list \
  CONFIG.PSU_BANK_0_IO_STANDARD.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_BANK_1_IO_STANDARD.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_BANK_2_IO_STANDARD.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_DDR_RAM_HIGHADDR.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_0_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_0_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_0_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_0_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_0_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_10_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_10_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_10_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_10_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_10_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_11_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_11_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_11_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_11_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_11_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_12_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_12_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_12_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_12_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_12_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_13_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_13_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_13_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_13_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_13_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_14_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_14_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_14_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_14_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_14_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_15_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_15_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_15_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_15_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_15_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_16_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_16_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_16_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_16_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_16_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_17_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_17_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_17_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_17_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_17_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_18_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_18_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_18_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_18_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_18_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_19_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_19_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_19_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_19_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_19_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_1_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_1_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_1_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_1_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_1_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_20_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_20_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_20_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_20_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_20_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_21_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_21_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_21_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_21_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_21_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_22_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_22_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_22_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_22_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_22_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_23_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_23_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_23_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_23_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_23_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_24_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_24_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_24_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_24_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_24_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_25_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_25_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_25_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_25_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_25_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_26_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_26_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_26_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_26_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_26_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_27_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_27_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_27_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_27_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_27_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_28_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_28_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_28_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_28_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_28_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_29_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_29_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_29_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_29_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_29_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_2_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_2_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_2_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_2_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_2_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_30_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_30_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_30_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_30_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_30_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_31_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_31_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_31_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_31_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_31_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_32_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_32_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_32_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_32_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_32_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_33_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_33_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_33_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_33_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_33_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_34_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_34_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_34_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_34_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_34_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_35_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_35_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_35_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_35_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_35_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_36_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_36_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_36_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_36_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_36_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_37_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_37_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_37_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_37_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_37_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_38_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_38_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_38_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_38_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_38_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_39_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_39_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_39_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_39_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_39_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_3_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_3_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_3_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_3_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_3_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_40_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_40_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_40_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_40_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_40_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_41_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_41_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_41_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_41_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_41_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_42_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_42_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_42_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_42_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_42_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_43_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_43_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_43_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_43_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_43_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_44_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_44_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_44_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_44_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_44_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_45_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_45_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_45_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_45_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_45_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_46_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_46_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_46_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_46_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_46_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_47_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_47_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_47_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_47_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_47_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_48_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_48_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_48_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_48_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_48_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_49_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_49_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_49_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_49_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_49_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_4_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_4_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_4_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_4_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_4_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_50_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_50_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_50_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_50_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_50_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_51_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_51_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_51_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_51_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_51_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_52_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_52_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_52_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_52_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_52_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_53_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_53_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_53_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_53_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_53_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_54_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_54_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_54_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_54_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_54_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_55_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_55_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_55_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_55_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_55_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_56_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_56_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_56_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_56_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_56_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_57_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_57_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_57_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_57_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_57_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_58_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_58_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_58_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_58_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_58_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_59_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_59_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_59_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_59_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_59_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_5_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_5_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_5_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_5_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_5_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_60_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_60_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_60_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_60_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_60_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_61_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_61_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_61_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_61_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_61_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_62_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_62_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_62_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_62_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_62_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_63_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_63_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_63_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_63_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_63_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_64_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_64_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_64_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_64_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_64_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_65_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_65_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_65_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_65_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_65_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_66_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_66_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_66_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_66_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_66_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_67_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_67_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_67_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_67_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_67_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_68_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_68_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_68_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_68_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_68_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_69_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_69_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_69_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_69_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_69_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_6_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_6_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_6_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_6_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_6_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_70_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_70_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_70_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_70_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_70_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_71_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_71_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_71_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_71_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_71_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_72_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_72_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_72_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_72_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_72_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_73_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_73_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_73_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_73_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_73_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_74_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_74_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_74_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_74_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_74_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_75_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_75_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_75_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_75_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_75_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_76_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_76_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_76_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_76_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_76_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_77_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_77_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_77_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_77_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_77_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_7_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_7_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_7_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_7_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_7_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_8_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_8_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_8_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_8_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_8_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_9_DIRECTION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_9_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_9_INPUT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_9_PULLUPDOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_9_SLEW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_TREE_PERIPHERALS.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_MIO_TREE_SIGNALS.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_PACKAGE_DDR_BOARD_DELAY3.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_PRESET_BANK0_VOLTAGE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_PRESET_BANK1_VOLTAGE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU_UIPARAM_GENERATE_SUMMARY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ACPU0__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ACPU1__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ACPU2__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ACPU3__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ACT_DDR_FREQ_MHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ADMA_COHERENCY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__AUX_REF_CLK__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CAN0__GRP_CLK__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CAN0__GRP_CLK__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CAN0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CAN0__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CAN1__GRP_CLK__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CAN1__GRP_CLK__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CPU_CPU_6X4X_MAX_RANGE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CPU_R5__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__ACPU__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__APM_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DFT125_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DFT125_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DFT250_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DFT250_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DFT270_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DFT270_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DFT300_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DFT300_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__GPU__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__AFI6__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__AMS__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__OCM_MAIN__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CRYSTAL__PERIPHERAL__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU_COHERENCY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_0__RESPONSE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_10__RESPONSE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_11__RESPONSE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_12__RESPONSE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_1__RESPONSE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_2__RESPONSE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_3__RESPONSE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_4__RESPONSE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_5__RESPONSE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_6__RESPONSE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_7__RESPONSE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_8__RESPONSE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__CSU_TAMPER_9__RESPONSE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__CSU__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DAP_COHERENCY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__BOARD_DELAY0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__BOARD_DELAY1.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__BOARD_DELAY2.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__BOARD_DELAY3.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__CLOCK_0_LENGTH_MM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__CLOCK_0_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__CLOCK_0_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__CLOCK_1_LENGTH_MM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__CLOCK_1_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__CLOCK_1_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__CLOCK_2_LENGTH_MM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__CLOCK_2_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__CLOCK_2_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__CLOCK_3_LENGTH_MM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__CLOCK_3_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__CLOCK_3_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DERATE_INT_D.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_0_LENGTH_MM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_0_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_0_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_1_LENGTH_MM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_1_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_1_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_2_LENGTH_MM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_2_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_2_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_3_LENGTH_MM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_3_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_3_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_0.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_1.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_2.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_3.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQ_0_LENGTH_MM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQ_0_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQ_0_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQ_1_LENGTH_MM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQ_1_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQ_1_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQ_2_LENGTH_MM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQ_2_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQ_2_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQ_3_LENGTH_MM.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQ_3_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__DQ_3_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__ECC_SCRUB.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__EN_2ND_CLK.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__HIGH_TEMP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__PARTNO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__PLL_BYPASS.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__PWR_DOWN_EN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__USE_INTERNAL_VREF.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DDR__INTERFACE__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DISPLAYPORT__LANE0__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DISPLAYPORT__LANE1__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DPAUX__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__DP__LANE_SEL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ENET0__GRP_MDIO__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ENET0__GRP_MDIO__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ENET0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ENET0__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ENET1__GRP_MDIO__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ENET1__GRP_MDIO__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ENET1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ENET1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ENET2__GRP_MDIO__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ENET2__GRP_MDIO__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ENET2__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__ENET2__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__FP__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEM0_COHERENCY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEM1_COHERENCY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEM2_COHERENCY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEM3_COHERENCY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEM__TSU__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEM__TSU__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GENERATE_SECURITY_REGISTERS.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEN_IPI_0__MASTER.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEN_IPI_10__MASTER.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEN_IPI_1__MASTER.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEN_IPI_2__MASTER.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEN_IPI_3__MASTER.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEN_IPI_4__MASTER.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEN_IPI_5__MASTER.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEN_IPI_6__MASTER.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEN_IPI_7__MASTER.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEN_IPI_8__MASTER.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GEN_IPI_9__MASTER.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GPIO2_MIO__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GPIO_EMIO__WIDTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GPU_PP0__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GPU_PP1__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GT_REF_CLK__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__GT__LINK_SPEED.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__I2C0__GRP_INT__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__I2C0__GRP_INT__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__I2C1__GRP_INT__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__I2C1__GRP_INT__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__L2_BANK0__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__NAND_COHERENCY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__NAND__CHIP_ENABLE__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__NAND__DATA_STROBE__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__NAND__DATA_STROBE__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__NAND__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__NAND__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__NAND__READY_BUSY__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__NAND__READY_BUSY__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__OCM_BANK0__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__OCM_BANK1__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__OCM_BANK2__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__OCM_BANK3__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__ACS_VIOLATION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__AER_CAPABILITY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR0_64BIT.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR0_PREFETCHABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR0_SCALE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR0_SIZE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR0_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR0_VAL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR1_64BIT.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR1_ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR1_PREFETCHABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR1_SCALE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR1_SIZE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR1_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR1_VAL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR2_64BIT.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR2_ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR2_PREFETCHABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR2_SCALE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR2_SIZE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR2_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR2_VAL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR3_64BIT.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR3_ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR3_PREFETCHABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR3_SCALE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR3_SIZE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR3_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR3_VAL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR4_64BIT.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR4_ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR4_PREFETCHABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR4_SCALE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR4_SIZE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR4_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR4_VAL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR5_64BIT.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR5_ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR5_PREFETCHABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR5_SCALE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR5_SIZE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR5_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BAR5_VAL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BASE_CLASS_MENU.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__BRIDGE_BAR_INDICATOR.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__CAP_SLOT_IMPLEMENTED.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__CLASS_CODE_VALUE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__COMPLETER_ABORT.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__COMPLTION_TIMEOUT.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__ECRC_CHECK.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__ECRC_ERR.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__ECRC_GEN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__EROM_ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__EROM_SCALE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__EROM_SIZE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__EROM_VAL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__FLOW_CONTROL_ERR.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__INTERFACE_WIDTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__INTX_GENERATION.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__INTX_PIN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__LANE1__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__LANE2__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__LANE2__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__LANE3__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__LANE3__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__LEGACY_INTERRUPT.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__MC_BLOCKED_TLP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__MSIX_CAPABILITY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__MSIX_PBA_OFFSET.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__MSIX_TABLE_SIZE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__MSI_CAPABILITY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__MSI_MULTIPLE_MSG_CAPABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__MULTIHEADER.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__RECEIVER_ERR.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__RECEIVER_OVERFLOW.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__REVISION_ID.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__SUBSYSTEM_ID.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__SUB_CLASS_INTERFACE_MENU.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__SURPRISE_DOWN.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__USE_CLASS_CODE_LOOKUP_ASSISTANT.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PCIE__VENDOR_ID.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PJTAG__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PL__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU_COHERENCY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__EMIO_GPI__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__EMIO_GPO__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPI0__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPI0__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPI1__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPI1__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPI2__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPI2__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPI3__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPI3__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPI4__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPI4__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPI5__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPI5__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPO0__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPO0__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPO1__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPO1__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPO2__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPO2__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPO3__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPO3__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPO4__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPO4__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPO5__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__GPO5__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PMU__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__ANALOG.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__DDR.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__FPD.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__LPD.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__MIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__PLL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__SERDES.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__DYNAMIC__TOTAL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__ONCHIP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__ANALOG.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__DDR.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__FPD.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__LPD.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__MIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__PLL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__SERDES.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER_SUMMARY__STATIC__TOTAL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__ACPU__VCCPSINTFP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__AFI_FPD__VCCPSINTFP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__AFI_LPD__VCCPSINTLP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__APLL__VCCPSPLL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__CAN0__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__CAN1__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__CSU__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__DDR__VCCPSDDR.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__DDR__VCCPSINTFP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__DPAUX__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__DPLL__VCCPSPLL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__DP__VCCPSGTA.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__DP__VCCPSINTFP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__FPINT__VCCPSINTFP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__GEM0__VCCPSINTLP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__GEM0__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__GEM1__VCCPSINTLP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__GEM1__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__GEM2__VCCPSINTLP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__GEM2__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__GEM3__VCCPSINTLP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__GEM3__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__GPIO0__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__GPIO1__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__GPIO2__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__GPU__VCCPSINTFP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__IOPLL__VCCPSPLL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__LPINT__VCCPSINTLP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__NAND__VCCPSINTLP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__NAND__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__PCIE__VCCPSGTA.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__PCIE__VCCPSINTFP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__PJTAG__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__PMU__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__QSPI__VCCPSINTLP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__QSPI__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__RPLL__VCCPSPLL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__RPU__VCCPSINTLP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__SATA__VCCPSGTA.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__SATA__VCCPSINTFP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__SD0__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__SD1__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__SGMII__VCCPSGTA.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__SPI0__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__SPI1__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__TRACE__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__TTC0__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__TTC1__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__TTC2__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__TTC3__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__UART0__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__UART1__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__USB0__VCCPSINTLP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__USB0__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__USB1__VCCPSINTLP.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__USB1__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__USB3__VCCPSGTA.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__VPLL__VCCPSPLL.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__WDT0__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__POWER__WDT1__VCCPSIO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__QSPI_COHERENCY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__RPU_COHERENCY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__RPU__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SATA__LANE0__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SATA__LANE0__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SD0_COHERENCY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SD0__DATA_TRANSFER_MODE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SD0__GRP_CD__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SD0__GRP_CD__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SD0__GRP_POW__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SD0__GRP_POW__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SD0__GRP_WP__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SD0__GRP_WP__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SD0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SD0__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SD0__RESET__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SD0__SLOT_TYPE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SD1_COHERENCY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SD1__RESET__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI0__GRP_SS0__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI0__GRP_SS0__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI0__GRP_SS1__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI0__GRP_SS1__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI0__GRP_SS2__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI0__GRP_SS2__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI0__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI1__GRP_SS0__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI1__GRP_SS0__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI1__GRP_SS1__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI1__GRP_SS1__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI1__GRP_SS2__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI1__GRP_SS2__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SPI1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SWDT0__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__SWDT1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__TCM0A__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__TCM0B__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__TCM1A__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__TCM1B__POWER__ON.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__TRACE__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__TRACE__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__TRACE__WIDTH.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__TRISTATE__INVERTED.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__TTC1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__TTC1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__TTC2__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__TTC2__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__TTC3__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__TTC3__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__UART0_LOOP_UART1__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__UART0__BAUD_RATE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__UART0__MODEM__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__UART1__BAUD_RATE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__USB0_COHERENCY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__USB1_COHERENCY.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__USB1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__USB1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__USB3_1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__USE__FABRIC__RST.VALUE_SRC {DEFAULT} \
  CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ.VALUE_SRC {DEFAULT} \
] [get_bd_cells sys_ps8]


set_property CONFIG.PSU__USE__M_AXI_GP2 {1} $sys_ps8
set_property CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} $sys_ps8
set_property CONFIG.PSU__FPGA_PL0_ENABLE {1} $sys_ps8
set_property CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} $sys_ps8
set_property CONFIG.PSU__FPGA_PL1_ENABLE {1} $sys_ps8
set_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {200} $sys_ps8
set_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {3} $sys_ps8
set_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {2} $sys_ps8
set_property CONFIG.PSU__USE__IRQ0 {1} $sys_ps8
set_property CONFIG.PSU__USE__IRQ1 {1} $sys_ps8
set_property CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} $sys_ps8

set_property -dict [list\
  CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \
  CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
  CONFIG.PSU__SPI1__PERIPHERAL__IO {EMIO} \
] [get_bd_cells sys_ps8]

set_property -dict [list\
  CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {100} \
  CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {100} \
] [get_bd_cells sys_ps8]

ad_ip_instance proc_sys_reset sys_rstgen
ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1

# system reset/clock definitions

ad_connect  sys_cpu_clk sys_ps8/pl_clk0
ad_connect  sys_200m_clk sys_ps8/pl_clk1
ad_connect  sys_cpu_reset sys_rstgen/peripheral_reset
ad_connect  sys_cpu_resetn sys_rstgen/peripheral_aresetn
ad_connect  sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect  sys_ps8/pl_resetn0 sys_rstgen/ext_reset_in

# gpio

ad_connect  gpio_i sys_ps8/emio_gpio_i
ad_connect  gpio_o sys_ps8/emio_gpio_o

# spi

ad_connect  sys_ps8/emio_spi0_ss_o_n spi0_csn
ad_connect  sys_ps8/emio_spi0_sclk_o spi0_sclk
ad_connect  sys_ps8/emio_spi0_m_o spi0_mosi
ad_connect  sys_ps8/emio_spi0_m_i spi0_miso
ad_connect  sys_ps8/emio_spi0_ss_i_n VCC
ad_connect  sys_ps8/emio_spi0_sclk_i GND
ad_connect  sys_ps8/emio_spi0_s_i GND

ad_connect  sys_ps8/emio_spi1_ss_o_n spi1_csn
ad_connect  sys_ps8/emio_spi1_sclk_o spi1_sclk
ad_connect  sys_ps8/emio_spi1_m_o spi1_mosi
ad_connect  sys_ps8/emio_spi1_m_i spi1_miso
ad_connect  sys_ps8/emio_spi1_ss_i_n VCC
ad_connect  sys_ps8/emio_spi1_sclk_i GND
ad_connect  sys_ps8/emio_spi1_s_i GND

# interrupts

ad_ip_instance xlconcat sys_concat_intc_0
ad_ip_parameter sys_concat_intc_0 CONFIG.NUM_PORTS 8

ad_ip_instance xlconcat sys_concat_intc_1
ad_ip_parameter sys_concat_intc_1 CONFIG.NUM_PORTS 8

ad_connect  sys_concat_intc_0/dout sys_ps8/pl_ps_irq0
ad_connect  sys_concat_intc_1/dout sys_ps8/pl_ps_irq1

ad_connect  sys_concat_intc_1/In7 ps_intr_15
ad_connect  sys_concat_intc_1/In6 ps_intr_14
ad_connect  sys_concat_intc_1/In5 ps_intr_13
ad_connect  sys_concat_intc_1/In4 ps_intr_12
ad_connect  sys_concat_intc_1/In3 ps_intr_11
ad_connect  sys_concat_intc_1/In2 ps_intr_10
ad_connect  sys_concat_intc_1/In1 ps_intr_09
ad_connect  sys_concat_intc_1/In0 ps_intr_08
ad_connect  sys_concat_intc_0/In7 ps_intr_07
ad_connect  sys_concat_intc_0/In6 ps_intr_06
ad_connect  sys_concat_intc_0/In5 ps_intr_05
ad_connect  sys_concat_intc_0/In4 ps_intr_04
ad_connect  sys_concat_intc_0/In3 ps_intr_03
ad_connect  sys_concat_intc_0/In2 ps_intr_02
ad_connect  sys_concat_intc_0/In1 ps_intr_01
ad_connect  sys_concat_intc_0/In0 ps_intr_00