2015-06-26 09:04:19 +00:00
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
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source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
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p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128
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p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
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create_bd_port -dir I -type rst sys_rst
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
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set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
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ad_connect sys_rst axi_ad9680_fifo/sys_rst
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ad_connect sys_clk axi_ad9680_fifo/sys_clk
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ad_connect ddr3 axi_ad9680_fifo/ddr3
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create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
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[get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \
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[get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \
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SEG_axi_ddr_cntrl_memaddr
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source ../common/daq2_bd.tcl
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