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pluto_hdl_adi/projects/adrv9009/zcu102/system_bd.tcl

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Renamed ad9379 to adrv9009
2018-04-25 13:02:59 +00:00
adrv9009/zcu102: Increase DAC buffer depth to 18Mb
2018-09-05 08:32:28 +00:00
## FIFO depth is 18Mb - 1M samples
set dac_fifo_address_width 17
Renamed ad9379 to adrv9009
2018-04-25 13:02:59 +00:00
adrv9009/zcu102: Increase DAC buffer depth to 18Mb
2018-09-05 08:32:28 +00:00
## NOTE: With this configuration the #36Kb BRAM utilization is at ~57%
Renamed ad9379 to adrv9009
2018-04-25 13:02:59 +00:00
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
adrv9009: Improved data throughput and DAC FIFO size Moved XCVR related connections to HP0, where the HP shares the MUX with the Video DMA HP1 and HP2 are used for RX OS and RX DMAs, sharing the MUX. Usually they shouldn't run at the same time. HP3 is used for TX DMA, sharing the MUX with the FPD DMA controller All HPx and DMA buswidths have been increased to 128 bits The HPx-DMA clock has been increased to 300 MHz DAC FIFO address size has been increased to 17
2018-05-11 12:01:05 +00:00
ad_mem_hp0_interconnect sys_cpu_clk sys_ps8/S_AXI_HP0
Renamed ad9379 to adrv9009
2018-04-25 13:02:59 +00:00
source ../common/adrv9009_bd.tcl
adrv9009: Improved data throughput and DAC FIFO size Moved XCVR related connections to HP0, where the HP shares the MUX with the Video DMA HP1 and HP2 are used for RX OS and RX DMAs, sharing the MUX. Usually they shouldn't run at the same time. HP3 is used for TX DMA, sharing the MUX with the FPD DMA controller All HPx and DMA buswidths have been increased to 128 bits The HPx-DMA clock has been increased to 300 MHz DAC FIFO address size has been increased to 17
2018-05-11 12:01:05 +00:00
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_DATA_WIDTH_DEST 128
adrv9009: Increase DMA FIFO sizes
2018-05-24 06:38:59 +00:00
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.FIFO_SIZE 32
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.FIFO_SIZE 32
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.FIFO_SIZE 32
adrv9009: Improved data throughput and DAC FIFO size Moved XCVR related connections to HP0, where the HP shares the MUX with the Video DMA HP1 and HP2 are used for RX OS and RX DMAs, sharing the MUX. Usually they shouldn't run at the same time. HP3 is used for TX DMA, sharing the MUX with the FPD DMA controller All HPx and DMA buswidths have been increased to 128 bits The HPx-DMA clock has been increased to 300 MHz DAC FIFO address size has been increased to 17
2018-05-11 12:01:05 +00:00
adrv9009: Increase sys_dma_clk to 325MHz. At 333 MHz, there are timing violations
2018-05-24 06:32:55 +00:00
ad_ip_instance clk_wiz dma_clk_wiz
adrv9009: Increased DMA clock frequency to ~333 MHz, by enabling AXI SLICES for DMAs
2018-06-07 14:29:52 +00:00
ad_ip_parameter dma_clk_wiz CONFIG.PRIMITIVE MMCM
adrv9009: Increase sys_dma_clk to 325MHz. At 333 MHz, there are timing violations
2018-05-24 06:32:55 +00:00
ad_ip_parameter dma_clk_wiz CONFIG.RESET_TYPE ACTIVE_LOW
ad_ip_parameter dma_clk_wiz CONFIG.USE_LOCKED false
adrv9009: Increased DMA clock frequency to ~333 MHz, by enabling AXI SLICES for DMAs
2018-06-07 14:29:52 +00:00
ad_ip_parameter dma_clk_wiz CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 332.9
adrv9009: Increase sys_dma_clk to 325MHz. At 333 MHz, there are timing violations
2018-05-24 06:32:55 +00:00
ad_ip_parameter dma_clk_wiz CONFIG.PRIM_SOURCE No_buffer
ad_connect sys_cpu_clk dma_clk_wiz/clk_in1
ad_connect sys_cpu_resetn dma_clk_wiz/resetn
ad_connect sys_dma_clk dma_clk_wiz/clk_out1
Renamed ad9379 to adrv9009
2018-04-25 13:02:59 +00:00
ad_connect sys_dma_rstgen/ext_reset_in sys_rstgen/peripheral_reset
ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.XCVR_TYPE 2
ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.XCVR_TYPE 2
ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.XCVR_TYPE 2
ad_ip_parameter util_adrv9009_xcvr CONFIG.XCVR_TYPE 2
ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 80
ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter axi_adrv9009_rx_clkgen CONFIG.DEVICE_TYPE 2
ad_ip_parameter axi_adrv9009_tx_clkgen CONFIG.DEVICE_TYPE 2