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pluto_hdl_adi/projects/cftl_std/zed/system_constr.xdc

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cftl_xil_zed: Initial commit for common platform used with CFTL circuits This common platform uses PS7 SPI and I2C to communicate with different chips. On different connectors different pin configurations are supported: - On connector JA, a spi interface and a 2 pin GPIO - On connector JB, a I2C interface - On connector JC, a spi interface with 2 chip selects
2015-01-09 15:41:24 +00:00
# CFTL
cftl_std: Added in the constraint file comments regarding supported CFTLs
2015-01-29 14:27:43 +00:00
#port compatible with: CN0179, CN0216, CN10326, CN0354, CN0355
cftl_std: Updated project. Switched to PS7 gpio. Renamed signals.
2015-01-23 12:11:33 +00:00
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports spi0_csn]; # "JA1"
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports spi0_mosi]; # "JA2"
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports spi0_miso]; # "JA3"
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports spi0_clk]; # "JA4"
set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33} [get_ports gpio_cftl[0]]; # "JA9"
set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports gpio_cftl[1]]; # "JA10"
cftl_xil_zed: Initial commit for common platform used with CFTL circuits This common platform uses PS7 SPI and I2C to communicate with different chips. On different connectors different pin configurations are supported: - On connector JA, a spi interface and a 2 pin GPIO - On connector JB, a I2C interface - On connector JC, a spi interface with 2 chip selects
2015-01-09 15:41:24 +00:00
cftl_std: Added in the constraint file comments regarding supported CFTLs
2015-01-29 14:27:43 +00:00
#port compatible with: CN0346, CN0349
cftl_std: Updated project. Switched to PS7 gpio. Renamed signals.
2015-01-23 12:11:33 +00:00
set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports iic_cftl_scl_io]; # "JB3"
set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports iic_cftl_sda_io]; # "JB4"
cftl_xil_zed: Initial commit for common platform used with CFTL circuits This common platform uses PS7 SPI and I2C to communicate with different chips. On different connectors different pin configurations are supported: - On connector JA, a spi interface and a 2 pin GPIO - On connector JB, a I2C interface - On connector JC, a spi interface with 2 chip selects
2015-01-09 15:41:24 +00:00
cftl_std: Added in the constraint file comments regarding supported CFTLs
2015-01-29 14:27:43 +00:00
#port compatible with: CN0179, CN0357
cftl_std: Updated project. Switched to PS7 gpio. Renamed signals.
2015-01-23 12:11:33 +00:00
set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports spi1_csn0]; # "JC1_P"
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports spi1_mosi]; # "JC1_N"
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports spi1_miso]; # "JC2_P"
set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports spi1_clk]; # "JC2_N"
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports spi1_csn1]; # "JC4_N"