2017-06-13 16:39:45 +00:00
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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2017-11-08 12:34:30 +00:00
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create_clock -period "4.000 ns" -name ref_clk [get_ports {ref_clk}]
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2017-06-13 16:39:45 +00:00
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derive_pll_clocks
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derive_clock_uncertainty
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2017-06-14 18:40:23 +00:00
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set_false_path -to [get_registers *sysref_en_m1*]
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2017-06-13 16:39:45 +00:00
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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2017-10-06 07:46:22 +00:00
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# flash interface
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set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_addr[*]} ]
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set_input_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_data[*]} ]
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set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_data[*]} ]
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set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_cen[*]} ]
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set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_oen} ]
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set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_resetn} ]
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set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_wen} ]
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set_false_path -from * -to [get_ports {flash_resetn}]
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