2015-05-01 15:48:09 +00:00
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# prcfg io
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create_bd_port -dir O clk
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2015-10-13 08:37:44 +00:00
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create_bd_port -dir O core_dac_i0_enable
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create_bd_port -dir O core_dac_q0_enable
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create_bd_port -dir O core_dac_i1_enable
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create_bd_port -dir O core_dac_q1_enable
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2016-11-21 14:45:10 +00:00
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create_bd_port -dir O core_dac_i0_valid
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create_bd_port -dir O core_dac_q0_valid
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create_bd_port -dir O core_dac_i1_valid
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2015-10-13 08:37:44 +00:00
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create_bd_port -dir O core_dac_q1_valid
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2016-11-21 14:45:10 +00:00
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create_bd_port -dir I -from 15 -to 0 core_dac_i0_data
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create_bd_port -dir I -from 15 -to 0 core_dac_q0_data
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create_bd_port -dir I -from 15 -to 0 core_dac_i1_data
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create_bd_port -dir I -from 15 -to 0 core_dac_q1_data
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create_bd_port -dir I dma_dac_i0_enable
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create_bd_port -dir I dma_dac_q0_enable
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create_bd_port -dir I dma_dac_i1_enable
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create_bd_port -dir I dma_dac_q1_enable
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create_bd_port -dir I dma_dac_i0_valid
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create_bd_port -dir I dma_dac_q0_valid
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create_bd_port -dir I dma_dac_i1_valid
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create_bd_port -dir I dma_dac_q1_valid
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create_bd_port -dir O -from 15 -to 0 dma_dac_i0_data
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create_bd_port -dir O -from 15 -to 0 dma_dac_q0_data
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create_bd_port -dir O -from 15 -to 0 dma_dac_i1_data
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create_bd_port -dir O -from 15 -to 0 dma_dac_q1_data
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2015-10-13 08:37:44 +00:00
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create_bd_port -dir O core_adc_i0_enable
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create_bd_port -dir O core_adc_q0_enable
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create_bd_port -dir O core_adc_i1_enable
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create_bd_port -dir O core_adc_q1_enable
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2016-11-21 14:45:10 +00:00
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create_bd_port -dir O core_adc_i0_valid
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create_bd_port -dir O core_adc_q0_valid
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create_bd_port -dir O core_adc_i1_valid
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2015-10-13 08:37:44 +00:00
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create_bd_port -dir O core_adc_q1_valid
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2016-11-21 14:45:10 +00:00
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create_bd_port -dir O -from 15 -to 0 core_adc_i0_data
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create_bd_port -dir O -from 15 -to 0 core_adc_q0_data
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create_bd_port -dir O -from 15 -to 0 core_adc_i1_data
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create_bd_port -dir O -from 15 -to 0 core_adc_q1_data
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2015-10-13 08:37:44 +00:00
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2016-11-21 14:45:10 +00:00
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create_bd_port -dir I dma_adc_i0_enable
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create_bd_port -dir I dma_adc_q0_enable
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create_bd_port -dir I dma_adc_i1_enable
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create_bd_port -dir I dma_adc_q1_enable
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create_bd_port -dir I dma_adc_i0_valid
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create_bd_port -dir I dma_adc_q0_valid
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create_bd_port -dir I dma_adc_i1_valid
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create_bd_port -dir I dma_adc_q1_valid
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create_bd_port -dir I -from 15 -to 0 dma_adc_i0_data
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create_bd_port -dir I -from 15 -to 0 dma_adc_q0_data
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create_bd_port -dir I -from 15 -to 0 dma_adc_i1_data
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create_bd_port -dir I -from 15 -to 0 dma_adc_q1_data
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create_bd_port -dir I -from 31 -to 0 up_dac_gpio_in
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create_bd_port -dir I -from 31 -to 0 up_adc_gpio_in
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create_bd_port -dir O -from 31 -to 0 up_dac_gpio_out
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create_bd_port -dir O -from 31 -to 0 up_adc_gpio_out
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# re-wiring, split between ad9361 core & upack/cpack modules
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ad_connect axi_ad9361_clk clk
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ad_reconct util_ad9361_dac_upack/dac_enable_0 dma_dac_i0_enable
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ad_reconct util_ad9361_dac_upack/dac_enable_1 dma_dac_q0_enable
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ad_reconct util_ad9361_dac_upack/dac_enable_2 dma_dac_i1_enable
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ad_reconct util_ad9361_dac_upack/dac_enable_3 dma_dac_q1_enable
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ad_reconct util_ad9361_dac_upack/dac_valid_0 dma_dac_i0_valid
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ad_reconct util_ad9361_dac_upack/dac_valid_1 dma_dac_q0_valid
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ad_reconct util_ad9361_dac_upack/dac_valid_2 dma_dac_i1_valid
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ad_reconct util_ad9361_dac_upack/dac_valid_3 dma_dac_q1_valid
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ad_reconct util_ad9361_dac_upack/dac_data_0 dma_dac_i0_data
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ad_reconct util_ad9361_dac_upack/dac_data_1 dma_dac_q0_data
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ad_reconct util_ad9361_dac_upack/dac_data_2 dma_dac_i1_data
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ad_reconct util_ad9361_dac_upack/dac_data_3 dma_dac_q1_data
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ad_reconct axi_ad9361/dac_enable_i0 core_dac_i0_enable
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ad_reconct axi_ad9361/dac_enable_q0 core_dac_q0_enable
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ad_reconct axi_ad9361/dac_enable_i1 core_dac_i1_enable
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ad_reconct axi_ad9361/dac_enable_q1 core_dac_q1_enable
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ad_reconct axi_ad9361/dac_valid_i0 core_dac_i0_valid
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ad_reconct axi_ad9361/dac_valid_q0 core_dac_q0_valid
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ad_reconct axi_ad9361/dac_valid_i1 core_dac_i1_valid
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ad_reconct axi_ad9361/dac_valid_q1 core_dac_q1_valid
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ad_reconct axi_ad9361/dac_data_i0 core_dac_i0_data
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ad_reconct axi_ad9361/dac_data_q0 core_dac_q0_data
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ad_reconct axi_ad9361/dac_data_i1 core_dac_i1_data
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ad_reconct axi_ad9361/dac_data_q1 core_dac_q1_data
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ad_reconct util_ad9361_adc_fifo/din_enable_0 dma_adc_i0_enable
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ad_reconct util_ad9361_adc_fifo/din_enable_1 dma_adc_q0_enable
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ad_reconct util_ad9361_adc_fifo/din_enable_2 dma_adc_i1_enable
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ad_reconct util_ad9361_adc_fifo/din_enable_3 dma_adc_q1_enable
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ad_reconct util_ad9361_adc_fifo/din_valid_0 dma_adc_i0_valid
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ad_reconct util_ad9361_adc_fifo/din_valid_1 dma_adc_q0_valid
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ad_reconct util_ad9361_adc_fifo/din_valid_2 dma_adc_i1_valid
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ad_reconct util_ad9361_adc_fifo/din_valid_3 dma_adc_q1_valid
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ad_reconct util_ad9361_adc_fifo/din_data_0 dma_adc_i0_data
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ad_reconct util_ad9361_adc_fifo/din_data_1 dma_adc_q0_data
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ad_reconct util_ad9361_adc_fifo/din_data_2 dma_adc_i1_data
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ad_reconct util_ad9361_adc_fifo/din_data_3 dma_adc_q1_data
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ad_reconct axi_ad9361/adc_enable_i0 core_adc_i0_enable
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ad_reconct axi_ad9361/adc_enable_q0 core_adc_q0_enable
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ad_reconct axi_ad9361/adc_enable_i1 core_adc_i1_enable
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ad_reconct axi_ad9361/adc_enable_q1 core_adc_q1_enable
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ad_reconct axi_ad9361/adc_valid_i0 core_adc_i0_valid
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ad_reconct axi_ad9361/adc_valid_q0 core_adc_q0_valid
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ad_reconct axi_ad9361/adc_valid_i1 core_adc_i1_valid
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ad_reconct axi_ad9361/adc_valid_q1 core_adc_q1_valid
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ad_reconct axi_ad9361/adc_data_i0 core_adc_i0_data
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ad_reconct axi_ad9361/adc_data_q0 core_adc_q0_data
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ad_reconct axi_ad9361/adc_data_i1 core_adc_i1_data
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ad_reconct axi_ad9361/adc_data_q1 core_adc_q1_data
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ad_reconct axi_ad9361/up_dac_gpio_in up_dac_gpio_in
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ad_reconct axi_ad9361/up_adc_gpio_in up_adc_gpio_in
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ad_reconct axi_ad9361/up_dac_gpio_out up_dac_gpio_out
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ad_reconct axi_ad9361/up_adc_gpio_out up_adc_gpio_out
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2015-05-01 15:48:09 +00:00
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