70 lines
2.5 KiB
Tcl
70 lines
2.5 KiB
Tcl
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package require -exact qsys 13.0
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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set_module_property NAME util_cpack
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set_module_property DESCRIPTION "Channel Pack Utility"
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set_module_property VERSION 1.0
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set_module_property DISPLAY_NAME util_cpack
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# files
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add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
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set_fileset_property quartus_synth TOP_LEVEL util_cpack
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add_fileset_file util_cpack_mux.v VERILOG PATH util_cpack_mux.v
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add_fileset_file util_cpack_dsf.v VERILOG PATH util_cpack_dsf.v
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add_fileset_file util_cpack.v VERILOG PATH util_cpack.v TOP_LEVEL_FILE
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# parameters
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add_parameter CH_DW INTEGER 0
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set_parameter_property CH_DW DEFAULT_VALUE 32
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set_parameter_property CH_DW DISPLAY_NAME CH_DW
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set_parameter_property CH_DW TYPE INTEGER
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set_parameter_property CH_DW UNITS None
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set_parameter_property CH_DW HDL_PARAMETER true
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add_parameter CH_CNT INTEGER 0
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set_parameter_property CH_CNT DEFAULT_VALUE 8
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set_parameter_property CH_CNT DISPLAY_NAME CH_CNT
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set_parameter_property CH_CNT TYPE INTEGER
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set_parameter_property CH_CNT UNITS None
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set_parameter_property CH_CNT HDL_PARAMETER true
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# defaults
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ad_alt_intf clock adc_clk input 1
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ad_alt_intf signal adc_rst input 1
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ad_alt_intf signal adc_valid_0 input 1
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ad_alt_intf signal adc_enable_0 input 1
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ad_alt_intf signal adc_data_0 input CH_DW
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ad_alt_intf signal adc_valid_1 input 1
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ad_alt_intf signal adc_enable_1 input 1
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ad_alt_intf signal adc_data_1 input CH_DW
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ad_alt_intf signal adc_valid_2 input 1
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ad_alt_intf signal adc_enable_2 input 1
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ad_alt_intf signal adc_data_2 input CH_DW
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ad_alt_intf signal adc_valid_3 input 1
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ad_alt_intf signal adc_enable_3 input 1
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ad_alt_intf signal adc_data_3 input CH_DW
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ad_alt_intf signal adc_valid_4 input 1
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ad_alt_intf signal adc_enable_4 input 1
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ad_alt_intf signal adc_data_4 input CH_DW
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ad_alt_intf signal adc_valid_5 input 1
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ad_alt_intf signal adc_enable_5 input 1
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ad_alt_intf signal adc_data_5 input CH_DW
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ad_alt_intf signal adc_valid_6 input 1
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ad_alt_intf signal adc_enable_6 input 1
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ad_alt_intf signal adc_data_6 input CH_DW
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ad_alt_intf signal adc_valid_7 input 1
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ad_alt_intf signal adc_enable_7 input 1
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ad_alt_intf signal adc_data_7 input CH_DW
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ad_alt_intf signal adc_valid output 1
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ad_alt_intf signal adc_sync output 1
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ad_alt_intf signal adc_data output CH_CNT*CH_DW
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