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pluto_hdl_adi/projects/fmcadc2/common/fmcadc2_bd.tcl

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Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# ad9625
create_bd_port -dir I rx_ref_clk
create_bd_port -dir O rx_sync
create_bd_port -dir O rx_sysref
create_bd_port -dir I -from 7 -to 0 rx_data_p
create_bd_port -dir I -from 7 -to 0 rx_data_n
# adc peripherals
set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core]
fmcadc2: Updated common design to 2015.4
2016-03-15 13:26:05 +00:00
set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_jesd]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd
set axi_ad9625_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9625_gt]
fmcadc2: Update projecct to 2015.2.1 - updated to the new jesd framework
2015-09-25 14:25:32 +00:00
set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_gt
set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_ad9625_gt
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_0 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_1 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_2 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_3 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_4 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_4 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_4 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_5 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_5 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_5 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_6 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_6 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_6 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_7 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_7 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_7 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_ad9625_gt
set util_ad9625_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad9625_gt]
set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_ad9625_gt
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad9625_gt
set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_ad9625_gt
set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad9625_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_ad9625_gt
set_property -dict [list CONFIG.TX_ENABLE {0}] $util_ad9625_gt
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.ID {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9625_dma
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# connections (gt)
fmcadc2: Update projecct to 2015.2.1 - updated to the new jesd framework
2015-09-25 14:25:32 +00:00
ad_connect util_ad9625_gt/qpll_ref_clk rx_ref_clk
ad_connect util_ad9625_gt/cpll_ref_clk rx_ref_clk
ad_connect axi_ad9625_gt/gt_pll_0 util_ad9625_gt/gt_pll_0
ad_connect axi_ad9625_gt/gt_pll_1 util_ad9625_gt/gt_pll_1
ad_connect axi_ad9625_gt/gt_pll_2 util_ad9625_gt/gt_pll_2
ad_connect axi_ad9625_gt/gt_pll_3 util_ad9625_gt/gt_pll_3
ad_connect axi_ad9625_gt/gt_pll_4 util_ad9625_gt/gt_pll_4
ad_connect axi_ad9625_gt/gt_pll_5 util_ad9625_gt/gt_pll_5
ad_connect axi_ad9625_gt/gt_pll_6 util_ad9625_gt/gt_pll_6
ad_connect axi_ad9625_gt/gt_pll_7 util_ad9625_gt/gt_pll_7
ad_connect axi_ad9625_gt/gt_rx_0 util_ad9625_gt/gt_rx_0
ad_connect axi_ad9625_gt/gt_rx_1 util_ad9625_gt/gt_rx_1
ad_connect axi_ad9625_gt/gt_rx_2 util_ad9625_gt/gt_rx_2
ad_connect axi_ad9625_gt/gt_rx_3 util_ad9625_gt/gt_rx_3
ad_connect axi_ad9625_gt/gt_rx_4 util_ad9625_gt/gt_rx_4
ad_connect axi_ad9625_gt/gt_rx_5 util_ad9625_gt/gt_rx_5
ad_connect axi_ad9625_gt/gt_rx_6 util_ad9625_gt/gt_rx_6
ad_connect axi_ad9625_gt/gt_rx_7 util_ad9625_gt/gt_rx_7
ad_connect axi_ad9625_gt/gt_rx_ip_0 axi_ad9625_jesd/gt0_rx
ad_connect axi_ad9625_gt/gt_rx_ip_1 axi_ad9625_jesd/gt1_rx
ad_connect axi_ad9625_gt/gt_rx_ip_2 axi_ad9625_jesd/gt2_rx
ad_connect axi_ad9625_gt/gt_rx_ip_3 axi_ad9625_jesd/gt3_rx
ad_connect axi_ad9625_gt/gt_rx_ip_4 axi_ad9625_jesd/gt4_rx
ad_connect axi_ad9625_gt/gt_rx_ip_5 axi_ad9625_jesd/gt5_rx
ad_connect axi_ad9625_gt/gt_rx_ip_6 axi_ad9625_jesd/gt6_rx
ad_connect axi_ad9625_gt/gt_rx_ip_7 axi_ad9625_jesd/gt7_rx
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_0 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_1 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_2 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_3 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_4 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_5 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_6 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_7 axi_ad9625_jesd/rxencommaalign_out
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# connections (adc)
fmcadc2: Update projecct to 2015.2.1 - updated to the new jesd framework
2015-09-25 14:25:32 +00:00
ad_connect util_ad9625_gt/rx_p rx_data_p
ad_connect util_ad9625_gt/rx_n rx_data_n
ad_connect util_ad9625_gt/rx_sync rx_sync
ad_connect util_ad9625_gt/rx_ip_sysref rx_sysref
ad_connect util_ad9625_gt/rx_out_clk util_ad9625_gt/rx_clk
ad_connect util_ad9625_gt/rx_out_clk axi_ad9625_jesd/rx_core_clk
ad_connect util_ad9625_gt/rx_ip_rst axi_ad9625_jesd/rx_reset
ad_connect util_ad9625_gt/rx_ip_rst_done axi_ad9625_jesd/rx_reset_done
ad_connect util_ad9625_gt/rx_ip_sysref axi_ad9625_jesd/rx_sysref
ad_connect util_ad9625_gt/rx_ip_sync axi_ad9625_jesd/rx_sync
ad_connect util_ad9625_gt/rx_ip_sof axi_ad9625_jesd/rx_start_of_frame
ad_connect util_ad9625_gt/rx_ip_data axi_ad9625_jesd/rx_tdata
ad_connect util_ad9625_gt/rx_out_clk axi_ad9625_core/rx_clk
ad_connect util_ad9625_gt/rx_data axi_ad9625_core/rx_data
ad_connect axi_ad9625_core/adc_clk axi_ad9625_fifo/adc_clk
ad_connect axi_ad9625_fifo/adc_rst axi_ad9625_core/adc_rst
ad_connect axi_ad9625_core/adc_enable axi_ad9625_fifo/adc_wr
ad_connect axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata
ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk
ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk
ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data
ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready
ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# interconnect (cpu)
ad_cpu_interconnect 0x44A60000 axi_ad9625_gt
ad_cpu_interconnect 0x44A10000 axi_ad9625_core
ad_cpu_interconnect 0x44A91000 axi_ad9625_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9625_dma
# gt uses hp3, and 100MHz clock for both DRP and AXI4
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9625_gt/m_axi
# interconnect (mem/adc)
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_ad9625_dma/m_dest_axi
# interrupts
ad_cpu_interrupt ps-13 mb-12 axi_ad9625_dma/irq