96 lines
3.6 KiB
Tcl
96 lines
3.6 KiB
Tcl
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad469x_spi
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create_bd_port -dir O ad469x_spi_cnv
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create_bd_port -dir I ad469x_spi_busy
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
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set data_width $ad_project_params(DATA_WIDTH)
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set async_spi_clk $ad_project_params(ASYNC_SPI_CLK)
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set num_cs $ad_project_params(NUM_CS)
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set num_sdi $ad_project_params(NUM_SDI)
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set sdi_delay $ad_project_params(SDI_DELAY)
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set hier_spi_engine spi_ad469x
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spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $sdi_delay
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# To support the 1MSPS (SCLK == 80 MHz), set the spi clock to 160 MHz
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ad_ip_instance axi_clkgen spi_clkgen
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ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5
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ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
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ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
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ad_connect $sys_cpu_clk spi_clkgen/clk
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ad_connect spi_clk spi_clkgen/clk_0
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## to setup the sample rate of the system change the PULSE_PERIOD value
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## the acutal sample rate will be PULSE_PERIOD * (1/sys_cpu_clk)
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set sampling_cycle [expr int(ceil(double($spi_clk_ref_frequency * 1000000) / $adc_sampling_rate))]
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ad_ip_instance axi_pulse_gen ad469x_trigger_gen
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ad_ip_parameter ad469x_trigger_gen CONFIG.PULSE_PERIOD $sampling_cycle
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ad_ip_parameter ad469x_trigger_gen CONFIG.PULSE_WIDTH 1
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ad_connect spi_clk ad469x_trigger_gen/ext_clk
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ad_connect $sys_cpu_clk ad469x_trigger_gen/s_axi_aclk
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ad_connect sys_cpu_resetn ad469x_trigger_gen/s_axi_aresetn
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# trigger to BUSY's negative edge
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create_bd_cell -type module -reference sync_bits busy_sync
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create_bd_cell -type module -reference ad_edge_detect busy_capture
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set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture]
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ad_connect spi_clk busy_capture/clk
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ad_connect busy_capture/rst GND
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ad_connect busy_sync/out_resetn $hier_spi_engine/axi_regmap/spi_resetn
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ad_connect spi_clk busy_sync/out_clk
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ad_connect busy_sync/in_bits ad469x_spi_busy
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ad_connect busy_sync/out_bits busy_capture/in
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ad_connect busy_capture/out $hier_spi_engine/offload/trigger
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# dma to receive data stream
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ad_ip_instance axi_dmac axi_ad469x_dma
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ad_ip_parameter axi_ad469x_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad469x_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad469x_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad469x_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad469x_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad469x_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad469x_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad469x_dma CONFIG.DMA_DATA_WIDTH_SRC $data_width
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ad_ip_parameter axi_ad469x_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_connect sys_cpu_clk $hier_spi_engine/clk
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ad_connect spi_clk axi_ad469x_dma/s_axis_aclk
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ad_connect sys_cpu_resetn $hier_spi_engine/resetn
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ad_connect sys_cpu_resetn axi_ad469x_dma/m_dest_axi_aresetn
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ad_connect spi_clk $hier_spi_engine/spi_clk
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ad_connect $hier_spi_engine/m_spi ad469x_spi
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ad_connect axi_ad469x_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE
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ad_ip_instance util_vector_logic cnv_gate
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ad_ip_parameter cnv_gate CONFIG.C_SIZE 1
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ad_ip_parameter cnv_gate CONFIG.C_OPERATION {and}
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ad_connect cnv_gate/Op1 axi_ad469x_dma/s_axis_xfer_req
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ad_connect cnv_gate/Op2 ad469x_trigger_gen/pulse
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ad_connect cnv_gate/Res ad469x_spi_cnv
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ad_cpu_interconnect 0x44a00000 $hier_spi_engine/axi_regmap
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ad_cpu_interconnect 0x44a30000 axi_ad469x_dma
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ad_cpu_interconnect 0x44a70000 spi_clkgen
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ad_cpu_interconnect 0x44b00000 ad469x_trigger_gen
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ad_cpu_interrupt "ps-13" "mb-13" axi_ad469x_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" /$hier_spi_engine/irq
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad469x_dma/m_dest_axi
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