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pluto_hdl_adi/library/util_adcfifo/util_adcfifo_hw.tcl

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util_adcfifo: Put a limit on the read/write address from memory so there is no overflow Added altera component
2015-11-04 11:31:50 +00:00
altera- default to latest version
2017-05-12 17:25:17 +00:00
package require qsys
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow Added altera component
2015-11-04 11:31:50 +00:00
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
adc/dac-fifo altera cores
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ad_ip_create util_adcfifo {UTIL ADC FIFO Interface}
resolving conflicts
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set_module_property ELABORATION_CALLBACK p_util_adcfifo
# files
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ad_ip_files util_adcfifo [list\
util_adcfifo: Synchronize the ad_rst and use it as a synchronous reset This improvement will solve a couple of [DRC REQP-1839] warning: "The RAMB36E1 has an input control pin * which is driven by a register * that has an active asynchronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default."
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$ad_hdl_dir/library/common/ad_rst.v \
adc/dac-fifo altera cores
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$ad_hdl_dir/library/common/ad_axis_inf_rx.v \
util_adcfifo: Fix the address generation and read logic
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$ad_hdl_dir/library/util_cdc/sync_gray.v \
adc/dac-fifo altera cores
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util_adcfifo.v \
util_adcfifo_constr.sdc]
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow Added altera component
2015-11-04 11:31:50 +00:00
# parameters
adc/dac-fifo altera cores
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ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
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ad_ip_parameter FPGA_TECHNOLOGY INTEGER 1
adc/dac-fifo altera cores
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ad_ip_parameter ADC_DATA_WIDTH INTEGER 256
ad_ip_parameter DMA_DATA_WIDTH INTEGER 64
ad_ip_parameter DMA_READY_ENABLE INTEGER 1
ad_ip_parameter DMA_ADDRESS_WIDTH INTEGER 10
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow Added altera component
2015-11-04 11:31:50 +00:00
resolving conflicts
2017-05-17 20:18:53 +00:00
# elaborate
proc p_util_adcfifo {} {
# read parameters
set m_device_family [get_parameter_value "DEVICE_FAMILY"]
set m_adc_data_width [get_parameter_value "ADC_DATA_WIDTH"]
set m_dma_addr_width [get_parameter_value "DMA_ADDRESS_WIDTH"]
set m_dma_data_width [get_parameter_value "DMA_DATA_WIDTH"]
# altera memory
add_hdl_instance alt_mem_asym alt_mem_asym
set_instance_parameter_value alt_mem_asym DEVICE_FAMILY $m_device_family
set_instance_parameter_value alt_mem_asym A_ADDRESS_WIDTH 0
set_instance_parameter_value alt_mem_asym A_DATA_WIDTH $m_adc_data_width
set_instance_parameter_value alt_mem_asym B_ADDRESS_WIDTH $m_dma_addr_width
set_instance_parameter_value alt_mem_asym B_DATA_WIDTH $m_dma_data_width
# interfaces
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow Added altera component
2015-11-04 11:31:50 +00:00
resolving conflicts
2017-05-17 20:18:53 +00:00
ad_alt_intf clock adc_clk input 1 adc_clk
ad_alt_intf reset adc_rst input 1 if_adc_clk
ad_alt_intf signal adc_wr input 1 valid
ad_alt_intf signal adc_wdata input ADC_DATA_WIDTH data
ad_alt_intf signal adc_wovf output 1 ovf
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow Added altera component
2015-11-04 11:31:50 +00:00
resolving conflicts
2017-05-17 20:18:53 +00:00
ad_alt_intf clock dma_clk input 1 clk
ad_alt_intf signal dma_xfer_req input 1 xfer_req
ad_alt_intf signal dma_xfer_status output 4 xfer_status
util_adcfifo/util_dacfifo: bundle AXIS signals into bus for Intel
2019-05-16 07:09:15 +00:00
add_interface m_axis axi4stream start
set_interface_property m_axis associatedClock if_dma_clk
set_interface_property m_axis associatedReset if_adc_rst
add_interface_port m_axis dma_wr tvalid Output 1
add_interface_port m_axis dma_wready tready Input 1
add_interface_port m_axis dma_wdata tdata Output DMA_DATA_WIDTH
resolving conflicts
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}
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow Added altera component
2015-11-04 11:31:50 +00:00