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pluto_hdl_adi/library/util_dacfifo/util_dacfifo_hw.tcl

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adc/dac-fifo altera cores
2017-02-28 18:30:50 +00:00
Update Quartus Prime version from 19.3.0 to 20.1.0 adi_project_intel.tcl: Change quartus version to 20.1.0. library: Set qsys version so that IP instances won't require a specific version.
2021-02-25 09:41:57 +00:00
package require qsys 14.0
adc/dac-fifo altera cores
2017-02-28 18:30:50 +00:00
source ../scripts/adi_env.tcl
library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl
2018-08-14 10:08:06 +00:00
source ../scripts/adi_ip_intel.tcl
adc/dac-fifo altera cores
2017-02-28 18:30:50 +00:00
ad_ip_create util_dacfifo {UTIL DAC FIFO Interface}
ad_ip_files util_dacfifo [list\
$ad_hdl_dir/library/common/ad_mem.v \
util_dacfifo: Fix the reset logic of the module Both the DMA and DAC side should be in reset at the positive edge of the dma_xfer_req, so we can re-initialize the buffer.
2018-08-22 12:05:00 +00:00
$ad_hdl_dir/library/common/ad_mem_asym.v \
util_dacfifo: Integrate grey coder/decoder module The grey coder/decoder function was limited to 10 bits, and this resulted an unwanted limitation of the FIFO size. Using this module, the coder/decoder data width can be adjusted to the current address width.
2017-10-05 11:20:54 +00:00
$ad_hdl_dir/library/common/ad_b2g.v \
$ad_hdl_dir/library/common/ad_g2b.v \
adc/dac-fifo altera cores
2017-02-28 18:30:50 +00:00
util_dacfifo.v \
util_dacfifo: Fix the reset logic of the module Both the DMA and DAC side should be in reset at the positive edge of the dma_xfer_req, so we can re-initialize the buffer.
2018-08-22 12:05:00 +00:00
util_dacfifo_bypass.v \
adc/dac-fifo altera cores
2017-02-28 18:30:50 +00:00
util_dacfifo_constr.sdc]
# parameters
ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
ad_ip_parameter ADDRESS_WIDTH INTEGER 6
ad_ip_parameter DATA_WIDTH INTEGER 128
# interfaces
scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface
2018-08-14 13:53:45 +00:00
ad_interface clock dma_clk input 1 clk
ad_interface reset dma_rst input 1 if_dma_clk
ad_interface signal dma_xfer_req input 1 xfer_req
util_adcfifo/util_dacfifo: bundle AXIS signals into bus for Intel
2019-05-16 07:09:15 +00:00
add_interface s_axis axi4stream end
set_interface_property s_axis associatedClock if_dma_clk
set_interface_property s_axis associatedReset if_dma_rst
add_interface_port s_axis dma_valid tvalid Input 1
add_interface_port s_axis dma_xfer_last tlast Input 1
add_interface_port s_axis dma_ready tready Output 1
add_interface_port s_axis dma_data tdata Input DATA_WIDTH
adc/dac-fifo altera cores
2017-02-28 18:30:50 +00:00
scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface
2018-08-14 13:53:45 +00:00
ad_interface clock dac_clk input 1
ad_interface reset dac_rst input 1 if_dac_clk
ad_interface signal dac_valid input 1 valid
ad_interface signal dac_data output DATA_WIDTH data
ad_interface signal dac_xfer_out output 1 xfer_req
ad_interface signal dac_dunf output 1 unf
adc/dac-fifo altera cores
2017-02-28 18:30:50 +00:00
scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface
2018-08-14 13:53:45 +00:00
ad_interface signal bypass input 1 bypass
adc/dac-fifo altera cores
2017-02-28 18:30:50 +00:00