2019-10-31 14:56:21 +00:00
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create_bd_port -dir I ref_clk_c
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create_bd_port -dir I ref_clk_d
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create_bd_port -dir I core_clk_c
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create_bd_port -dir I core_clk_d
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2019-11-04 15:57:11 +00:00
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create_bd_port -dir I dac_fifo_bypass
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2019-10-31 14:56:21 +00:00
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# TX parameters
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set TX_NUM_OF_LANES 8 ; # L
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set TX_NUM_OF_CONVERTERS 8 ; # M
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set TX_SAMPLES_PER_FRAME 1 ; # S
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set TX_SAMPLE_WIDTH 16 ; # N/NP
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set TX_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
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# RX parameters
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set RX_NUM_OF_LANES 4 ; # L
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set RX_NUM_OF_CONVERTERS 8 ; # M
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set RX_SAMPLES_PER_FRAME 1 ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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set RX_SAMPLES_PER_CHANNEL 1 ; # L * 32 / (M * N)
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# RX Observation parameters
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set OBS_NUM_OF_LANES 4 ; # L
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set OBS_NUM_OF_CONVERTERS 4 ; # M
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set OBS_SAMPLES_PER_FRAME 1 ; # S
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set OBS_SAMPLE_WIDTH 16 ; # N/NP
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set OBS_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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2019-11-04 15:57:11 +00:00
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set dac_fifo_name axi_adrv9009_fmc_tx_fifo
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set dac_data_width 256
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set dac_dma_data_width 256
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ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
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2019-10-31 14:56:21 +00:00
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ad_ip_instance axi_adxcvr axi_adrv9009_fmc_tx_xcvr
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ad_ip_parameter axi_adrv9009_fmc_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_fmc_tx_xcvr CONFIG.QPLL_ENABLE 1
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ad_ip_parameter axi_adrv9009_fmc_tx_xcvr CONFIG.TX_OR_RX_N 1
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adi_axi_jesd204_tx_create axi_adrv9009_fmc_tx_jesd $TX_NUM_OF_LANES
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set_property -dict [list CONFIG.SYSREF_IOB {false}] [get_bd_cells axi_adrv9009_fmc_tx_jesd/tx]
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ad_ip_instance util_upack2 util_fmc_tx_upack [list \
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NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_tx_create tx_adrv9009_fmc_tpl_core $TX_NUM_OF_LANES \
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$TX_NUM_OF_CONVERTERS \
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$TX_SAMPLES_PER_FRAME \
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$TX_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_adrv9009_fmc_tx_dma
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_TYPE_DEST 1
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.CYCLIC 1
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_2D_TRANSFER 0
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2019-11-04 15:57:11 +00:00
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_DATA_WIDTH_DEST 256
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2019-10-31 14:56:21 +00:00
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.FIFO_SIZE 32
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.MAX_BYTES_PER_BURST 512
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ad_ip_instance axi_adxcvr axi_adrv9009_fmc_rx_xcvr
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ad_ip_parameter axi_adrv9009_fmc_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_fmc_rx_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_adrv9009_fmc_rx_xcvr CONFIG.TX_OR_RX_N 0
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adi_axi_jesd204_rx_create axi_adrv9009_fmc_rx_jesd $RX_NUM_OF_LANES
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ad_ip_instance util_cpack2 util_fmc_rx_cpack [list \
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NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_rx_create rx_adrv9009_fmc_tpl_core $RX_NUM_OF_LANES \
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$RX_NUM_OF_CONVERTERS \
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$RX_SAMPLES_PER_FRAME \
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$RX_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_adrv9009_fmc_rx_dma
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_instance axi_adxcvr axi_adrv9009_fmc_obs_xcvr
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ad_ip_parameter axi_adrv9009_fmc_obs_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_fmc_obs_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_adrv9009_fmc_obs_xcvr CONFIG.TX_OR_RX_N 0
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adi_axi_jesd204_rx_create axi_adrv9009_fmc_obs_jesd $OBS_NUM_OF_LANES
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ad_ip_instance util_cpack2 util_fmc_obs_cpack [list \
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NUM_OF_CHANNELS $OBS_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $OBS_SAMPLES_PER_CHANNEL\
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SAMPLE_DATA_WIDTH $OBS_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_rx_create obs_adrv9009_fmc_tpl_core $OBS_NUM_OF_LANES \
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$OBS_NUM_OF_CONVERTERS \
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$OBS_SAMPLES_PER_FRAME \
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$OBS_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_adrv9009_fmc_obs_dma
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_instance util_adxcvr util_adrv9009_fmc_xcvr
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.RX_NUM_OF_LANES [expr $RX_NUM_OF_LANES+$OBS_NUM_OF_LANES]
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.TX_OUT_DIV 2
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.CPLL_FBDIV 4
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.RX_CLK25_DIV 10
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.TX_CLK25_DIV 10
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.QPLL_FBDIV 80
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.QPLL_REFCLK_DIV 1
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ad_xcvrpll ref_clk_c util_adrv9009_fmc_xcvr/qpll_ref_clk_0
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ad_xcvrpll ref_clk_d util_adrv9009_fmc_xcvr/cpll_ref_clk_0
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ad_xcvrpll ref_clk_d util_adrv9009_fmc_xcvr/cpll_ref_clk_1
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ad_xcvrpll ref_clk_c util_adrv9009_fmc_xcvr/cpll_ref_clk_2
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ad_xcvrpll ref_clk_c util_adrv9009_fmc_xcvr/cpll_ref_clk_3
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ad_xcvrpll ref_clk_c util_adrv9009_fmc_xcvr/qpll_ref_clk_4
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ad_xcvrpll ref_clk_d util_adrv9009_fmc_xcvr/cpll_ref_clk_4
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ad_xcvrpll ref_clk_d util_adrv9009_fmc_xcvr/cpll_ref_clk_5
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ad_xcvrpll ref_clk_c util_adrv9009_fmc_xcvr/cpll_ref_clk_6
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ad_xcvrpll ref_clk_c util_adrv9009_fmc_xcvr/cpll_ref_clk_7
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ad_xcvrpll axi_adrv9009_fmc_tx_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_qpll_rst_0
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ad_xcvrpll axi_adrv9009_fmc_rx_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_0
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ad_xcvrpll axi_adrv9009_fmc_rx_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_1
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ad_xcvrpll axi_adrv9009_fmc_obs_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_2
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ad_xcvrpll axi_adrv9009_fmc_obs_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_3
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ad_xcvrpll axi_adrv9009_fmc_tx_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_qpll_rst_4
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ad_xcvrpll axi_adrv9009_fmc_rx_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_4
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ad_xcvrpll axi_adrv9009_fmc_rx_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_5
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ad_xcvrpll axi_adrv9009_fmc_obs_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_6
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ad_xcvrpll axi_adrv9009_fmc_obs_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_7
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ad_connect sys_cpu_resetn util_adrv9009_fmc_xcvr/up_rstn
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ad_connect sys_cpu_clk util_adrv9009_fmc_xcvr/up_clk
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2021-01-20 15:19:24 +00:00
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ad_xcvrcon util_adrv9009_fmc_xcvr axi_adrv9009_fmc_tx_xcvr axi_adrv9009_fmc_tx_jesd {1 0 2 3 4 5 6 7} core_clk_c
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2019-10-31 14:56:21 +00:00
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ad_xcvrcon util_adrv9009_fmc_xcvr axi_adrv9009_fmc_rx_xcvr axi_adrv9009_fmc_rx_jesd {0 1 4 5} core_clk_d
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ad_xcvrcon util_adrv9009_fmc_xcvr axi_adrv9009_fmc_obs_xcvr axi_adrv9009_fmc_obs_jesd {2 3 6 7} core_clk_c
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ad_connect core_clk_c tx_adrv9009_fmc_tpl_core/link_clk
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ad_connect axi_adrv9009_fmc_tx_jesd/tx_data tx_adrv9009_fmc_tpl_core/link
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ad_connect core_clk_c util_fmc_tx_upack/clk
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ad_connect core_clk_c_rstgen/peripheral_reset util_fmc_tx_upack/reset
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ad_connect tx_adrv9009_fmc_tpl_core/dac_valid_0 util_fmc_tx_upack/fifo_rd_en
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for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect util_fmc_tx_upack/fifo_rd_data_$i tx_adrv9009_fmc_tpl_core/dac_data_$i
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ad_connect tx_adrv9009_fmc_tpl_core/dac_enable_$i util_fmc_tx_upack/enable_$i
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}
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ad_connect tx_adrv9009_fmc_tpl_core/dac_dunf util_fmc_tx_upack/fifo_rd_underflow
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2019-11-04 15:57:11 +00:00
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ad_connect core_clk_c axi_adrv9009_fmc_tx_fifo/dac_clk
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ad_connect core_clk_c_rstgen/peripheral_reset axi_adrv9009_fmc_tx_fifo/dac_rst
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ad_connect util_fmc_tx_upack/s_axis_valid VCC
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ad_connect util_fmc_tx_upack/s_axis_ready axi_adrv9009_fmc_tx_fifo/dac_valid
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ad_connect util_fmc_tx_upack/s_axis_data axi_adrv9009_fmc_tx_fifo/dac_data
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ad_connect core_clk_c axi_adrv9009_fmc_tx_fifo/dma_clk
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ad_connect core_clk_c_rstgen/peripheral_reset axi_adrv9009_fmc_tx_fifo/dma_rst
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ad_connect core_clk_c axi_adrv9009_fmc_tx_dma/m_axis_aclk
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ad_connect axi_adrv9009_fmc_tx_fifo/dma_xfer_req axi_adrv9009_fmc_tx_dma/m_axis_xfer_req
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ad_connect axi_adrv9009_fmc_tx_fifo/dma_ready axi_adrv9009_fmc_tx_dma/m_axis_ready
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ad_connect axi_adrv9009_fmc_tx_fifo/dma_data axi_adrv9009_fmc_tx_dma/m_axis_data
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ad_connect axi_adrv9009_fmc_tx_fifo/dma_valid axi_adrv9009_fmc_tx_dma/m_axis_valid
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ad_connect axi_adrv9009_fmc_tx_fifo/dma_xfer_last axi_adrv9009_fmc_tx_dma/m_axis_last
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ad_connect axi_adrv9009_fmc_tx_fifo/bypass dac_fifo_bypass
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2019-10-31 14:56:21 +00:00
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ad_connect core_clk_d rx_adrv9009_fmc_tpl_core/link_clk
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ad_connect axi_adrv9009_fmc_rx_jesd/rx_sof rx_adrv9009_fmc_tpl_core/link_sof
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ad_connect axi_adrv9009_fmc_rx_jesd/rx_data_tdata rx_adrv9009_fmc_tpl_core/link_data
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ad_connect axi_adrv9009_fmc_rx_jesd/rx_data_tvalid rx_adrv9009_fmc_tpl_core/link_valid
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ad_connect core_clk_d util_fmc_rx_cpack/clk
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ad_connect core_clk_d_rstgen/peripheral_reset util_fmc_rx_cpack/reset
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ad_connect rx_adrv9009_fmc_tpl_core/adc_valid_0 util_fmc_rx_cpack/fifo_wr_en
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for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect rx_adrv9009_fmc_tpl_core/adc_enable_$i util_fmc_rx_cpack/enable_$i
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ad_connect rx_adrv9009_fmc_tpl_core/adc_data_$i util_fmc_rx_cpack/fifo_wr_data_$i
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}
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ad_connect rx_adrv9009_fmc_tpl_core/adc_dovf util_fmc_rx_cpack/fifo_wr_overflow
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ad_connect axi_adrv9009_fmc_rx_dma/fifo_wr util_fmc_rx_cpack/packed_fifo_wr
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ad_connect core_clk_d axi_adrv9009_fmc_rx_dma/fifo_wr_clk
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# connections (adc-os)
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ad_connect core_clk_c obs_adrv9009_fmc_tpl_core/link_clk
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ad_connect axi_adrv9009_fmc_obs_jesd/rx_sof obs_adrv9009_fmc_tpl_core/link_sof
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ad_connect axi_adrv9009_fmc_obs_jesd/rx_data_tdata obs_adrv9009_fmc_tpl_core/link_data
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ad_connect axi_adrv9009_fmc_obs_jesd/rx_data_tvalid obs_adrv9009_fmc_tpl_core/link_valid
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ad_connect core_clk_c util_fmc_obs_cpack/clk
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ad_connect core_clk_c_rstgen/peripheral_reset util_fmc_obs_cpack/reset
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ad_connect core_clk_c axi_adrv9009_fmc_obs_dma/fifo_wr_clk
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ad_connect obs_adrv9009_fmc_tpl_core/adc_valid_0 util_fmc_obs_cpack/fifo_wr_en
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for {set i 0} {$i < $OBS_NUM_OF_CONVERTERS} {incr i} {
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ad_connect obs_adrv9009_fmc_tpl_core/adc_enable_$i util_fmc_obs_cpack/enable_$i
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ad_connect obs_adrv9009_fmc_tpl_core/adc_data_$i util_fmc_obs_cpack/fifo_wr_data_$i
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}
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ad_connect obs_adrv9009_fmc_tpl_core/adc_dovf util_fmc_obs_cpack/fifo_wr_overflow
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ad_connect util_fmc_obs_cpack/packed_fifo_wr axi_adrv9009_fmc_obs_dma/fifo_wr
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ad_cpu_interconnect 0x45A00000 rx_adrv9009_fmc_tpl_core
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ad_cpu_interconnect 0x45A04000 tx_adrv9009_fmc_tpl_core
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ad_cpu_interconnect 0x45A08000 obs_adrv9009_fmc_tpl_core
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ad_cpu_interconnect 0x45A20000 axi_adrv9009_fmc_tx_xcvr
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ad_cpu_interconnect 0x45A30000 axi_adrv9009_fmc_tx_jesd
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ad_cpu_interconnect 0x45A40000 axi_adrv9009_fmc_rx_xcvr
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ad_cpu_interconnect 0x45A50000 axi_adrv9009_fmc_rx_jesd
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ad_cpu_interconnect 0x45A60000 axi_adrv9009_fmc_obs_xcvr
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ad_cpu_interconnect 0x45A70000 axi_adrv9009_fmc_obs_jesd
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ad_cpu_interconnect 0x7d400000 axi_adrv9009_fmc_tx_dma
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ad_cpu_interconnect 0x7d420000 axi_adrv9009_fmc_rx_dma
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ad_cpu_interconnect 0x7d440000 axi_adrv9009_fmc_obs_dma
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ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9009_fmc_rx_xcvr/m_axi
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ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9009_fmc_obs_xcvr/m_axi
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# interconnect (mem/dac)
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ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9009_fmc_tx_dma/m_src_axi
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ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9009_fmc_rx_dma/m_dest_axi
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ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9009_fmc_obs_dma/m_dest_axi
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ad_connect $sys_dma_resetn axi_adrv9009_fmc_rx_dma/m_dest_axi_aresetn
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ad_connect $sys_dma_resetn axi_adrv9009_fmc_tx_dma/m_src_axi_aresetn
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ad_connect $sys_dma_resetn axi_adrv9009_fmc_obs_dma/m_dest_axi_aresetn
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2020-02-28 14:54:26 +00:00
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ad_cpu_interrupt ps-8 mb-8 axi_adrv9009_fmc_obs_dma/irq
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ad_cpu_interrupt ps-9 mb-9 axi_adrv9009_fmc_tx_dma/irq
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ad_cpu_interrupt ps-10 mb-15 axi_adrv9009_fmc_rx_dma/irq
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ad_cpu_interrupt ps-11 mb-14 axi_adrv9009_fmc_obs_jesd/irq
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ad_cpu_interrupt ps-12 mb-13 axi_adrv9009_fmc_tx_jesd/irq
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ad_cpu_interrupt ps-13 mb-12 axi_adrv9009_fmc_rx_jesd/irq
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