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pluto_hdl_adi/projects/dac_fmc_ebz/zcu102/Makefile

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dac_fmc_ebz: Add initial ZCU102 and ZC706 carrier support Add a generic project for the AD91xx-FMC-EBZ DAC boards connected to the ZCU102 and ZC706 carrier boards. The project is called dac_fmc_ebz as the intention is to support all DAC FMC evaluation boards with this project since they are sufficiently similar to be supported by the same design. This project will successively extended to add support for more boards. The desired DAC device and JESD operation mode must be selected from the following file: ./common/config.tcl This design can support the following FMC boards which are all pin compatible: * AD9135-FMC-EBZ * AD9136-FMC-EBZ * AD9144-FMC-EBZ * AD9152-FMC-EBZ * AD9154-FMC-EBZ * AD916x-FMC-EBZ * AD9171-FMC-EBZ * AD9172-FMC-EBZ * AD9173-FMC-EBZ Note that the AD9152-FMC-EBZ only uses the first 4 lanes, whereas all other boards use 8 lanes. This project assumes that the transceiver reference clock and SYSREF are provided via the clock distribution chip that is found on the ADxxxx-FMC-EBZ board. In terms of pin connections between the FPGA and the FMC board the AD9172-FMC-EBZ is very similar to the AD9144-FMC-EBZ. The main differences are: * The DAC txen signals are connected to different pins * The polarity of the spi_en signal is active low instead of active high * The maximum lane rate is up to 15.4 Gpbs To accommodate this 5 txctrl signals as well as the spi_en signal are connected to GPIOs. Software can decide how to use them depending on which FMC board is connected. Note that each carrier has a maximum supported lane rate. Modes of the AD9172 (and similar) that exceed the carrier specific limit can not be used on that carrier. The limits are as following: * ZC706: 10.3125 Gbps * ZCU102: 15.4 Gbps (max AD9172 lanerate) * SPI and GPIOs to PMOD header support Connect a SPI interface and some GPIOs to the PL PMOD headers on the zcu102 and zc706 carriers. This is can be used to control additional external hardware like a clock chip or an analog front-end. This is especially useful on FMC boards that do not feature a clock generator chip. The pin out is: PMOD 1: SPI clock PMOD 2: SPI chipselect PMOD 3: SPI MOSI PMOD 4: SPI MISO PMOD 7: GPIO 0 PMOD 8: GPIO 1 PMOD 9: GPIO 2 PMOD 10: GPIO 3 The GPIOs are mapped at offset 48-51 of the EMIO GPIOs.
2018-06-15 11:50:34 +00:00
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := dac_fmc_ebz_zcu102
M_DEPS += ../common/dac_fmc_ebz_bd.tcl
dac_fmc_ebz: update Makefiles
2019-05-08 15:09:00 +00:00
M_DEPS += ../common/config.tcl
dac_fmc_ebz: Add initial ZCU102 and ZC706 carrier support Add a generic project for the AD91xx-FMC-EBZ DAC boards connected to the ZCU102 and ZC706 carrier boards. The project is called dac_fmc_ebz as the intention is to support all DAC FMC evaluation boards with this project since they are sufficiently similar to be supported by the same design. This project will successively extended to add support for more boards. The desired DAC device and JESD operation mode must be selected from the following file: ./common/config.tcl This design can support the following FMC boards which are all pin compatible: * AD9135-FMC-EBZ * AD9136-FMC-EBZ * AD9144-FMC-EBZ * AD9152-FMC-EBZ * AD9154-FMC-EBZ * AD916x-FMC-EBZ * AD9171-FMC-EBZ * AD9172-FMC-EBZ * AD9173-FMC-EBZ Note that the AD9152-FMC-EBZ only uses the first 4 lanes, whereas all other boards use 8 lanes. This project assumes that the transceiver reference clock and SYSREF are provided via the clock distribution chip that is found on the ADxxxx-FMC-EBZ board. In terms of pin connections between the FPGA and the FMC board the AD9172-FMC-EBZ is very similar to the AD9144-FMC-EBZ. The main differences are: * The DAC txen signals are connected to different pins * The polarity of the spi_en signal is active low instead of active high * The maximum lane rate is up to 15.4 Gpbs To accommodate this 5 txctrl signals as well as the spi_en signal are connected to GPIOs. Software can decide how to use them depending on which FMC board is connected. Note that each carrier has a maximum supported lane rate. Modes of the AD9172 (and similar) that exceed the carrier specific limit can not be used on that carrier. The limits are as following: * ZC706: 10.3125 Gbps * ZCU102: 15.4 Gbps (max AD9172 lanerate) * SPI and GPIOs to PMOD header support Connect a SPI interface and some GPIOs to the PL PMOD headers on the zcu102 and zc706 carriers. This is can be used to control additional external hardware like a clock chip or an analog front-end. This is especially useful on FMC boards that do not feature a clock generator chip. The pin out is: PMOD 1: SPI clock PMOD 2: SPI chipselect PMOD 3: SPI MOSI PMOD 4: SPI MISO PMOD 7: GPIO 0 PMOD 8: GPIO 1 PMOD 9: GPIO 2 PMOD 10: GPIO 3 The GPIOs are mapped at offset 48-51 of the EMIO GPIOs.
2018-06-15 11:50:34 +00:00
M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
library: Move ad_iobuf to the common library, as it's not Xilinx specific Updated all system_project and Makefiles
2020-09-23 08:30:18 +00:00
M_DEPS += ../../../library/common/ad_iobuf.v
dac_fmc_ebz: Add initial ZCU102 and ZC706 carrier support Add a generic project for the AD91xx-FMC-EBZ DAC boards connected to the ZCU102 and ZC706 carrier boards. The project is called dac_fmc_ebz as the intention is to support all DAC FMC evaluation boards with this project since they are sufficiently similar to be supported by the same design. This project will successively extended to add support for more boards. The desired DAC device and JESD operation mode must be selected from the following file: ./common/config.tcl This design can support the following FMC boards which are all pin compatible: * AD9135-FMC-EBZ * AD9136-FMC-EBZ * AD9144-FMC-EBZ * AD9152-FMC-EBZ * AD9154-FMC-EBZ * AD916x-FMC-EBZ * AD9171-FMC-EBZ * AD9172-FMC-EBZ * AD9173-FMC-EBZ Note that the AD9152-FMC-EBZ only uses the first 4 lanes, whereas all other boards use 8 lanes. This project assumes that the transceiver reference clock and SYSREF are provided via the clock distribution chip that is found on the ADxxxx-FMC-EBZ board. In terms of pin connections between the FPGA and the FMC board the AD9172-FMC-EBZ is very similar to the AD9144-FMC-EBZ. The main differences are: * The DAC txen signals are connected to different pins * The polarity of the spi_en signal is active low instead of active high * The maximum lane rate is up to 15.4 Gpbs To accommodate this 5 txctrl signals as well as the spi_en signal are connected to GPIOs. Software can decide how to use them depending on which FMC board is connected. Note that each carrier has a maximum supported lane rate. Modes of the AD9172 (and similar) that exceed the carrier specific limit can not be used on that carrier. The limits are as following: * ZC706: 10.3125 Gbps * ZCU102: 15.4 Gbps (max AD9172 lanerate) * SPI and GPIOs to PMOD header support Connect a SPI interface and some GPIOs to the PL PMOD headers on the zcu102 and zc706 carriers. This is can be used to control additional external hardware like a clock chip or an analog front-end. This is especially useful on FMC boards that do not feature a clock generator chip. The pin out is: PMOD 1: SPI clock PMOD 2: SPI chipselect PMOD 3: SPI MOSI PMOD 4: SPI MISO PMOD 7: GPIO 0 PMOD 8: GPIO 1 PMOD 9: GPIO 2 PMOD 10: GPIO 3 The GPIOs are mapped at offset 48-51 of the EMIO GPIOs.
2018-06-15 11:50:34 +00:00
LIB_DEPS += axi_dmac
Makefile: Update makefiles
2019-08-22 09:00:05 +00:00
LIB_DEPS += axi_sysid
dac_fmc_ebz: Add initial ZCU102 and ZC706 carrier support Add a generic project for the AD91xx-FMC-EBZ DAC boards connected to the ZCU102 and ZC706 carrier boards. The project is called dac_fmc_ebz as the intention is to support all DAC FMC evaluation boards with this project since they are sufficiently similar to be supported by the same design. This project will successively extended to add support for more boards. The desired DAC device and JESD operation mode must be selected from the following file: ./common/config.tcl This design can support the following FMC boards which are all pin compatible: * AD9135-FMC-EBZ * AD9136-FMC-EBZ * AD9144-FMC-EBZ * AD9152-FMC-EBZ * AD9154-FMC-EBZ * AD916x-FMC-EBZ * AD9171-FMC-EBZ * AD9172-FMC-EBZ * AD9173-FMC-EBZ Note that the AD9152-FMC-EBZ only uses the first 4 lanes, whereas all other boards use 8 lanes. This project assumes that the transceiver reference clock and SYSREF are provided via the clock distribution chip that is found on the ADxxxx-FMC-EBZ board. In terms of pin connections between the FPGA and the FMC board the AD9172-FMC-EBZ is very similar to the AD9144-FMC-EBZ. The main differences are: * The DAC txen signals are connected to different pins * The polarity of the spi_en signal is active low instead of active high * The maximum lane rate is up to 15.4 Gpbs To accommodate this 5 txctrl signals as well as the spi_en signal are connected to GPIOs. Software can decide how to use them depending on which FMC board is connected. Note that each carrier has a maximum supported lane rate. Modes of the AD9172 (and similar) that exceed the carrier specific limit can not be used on that carrier. The limits are as following: * ZC706: 10.3125 Gbps * ZCU102: 15.4 Gbps (max AD9172 lanerate) * SPI and GPIOs to PMOD header support Connect a SPI interface and some GPIOs to the PL PMOD headers on the zcu102 and zc706 carriers. This is can be used to control additional external hardware like a clock chip or an analog front-end. This is especially useful on FMC boards that do not feature a clock generator chip. The pin out is: PMOD 1: SPI clock PMOD 2: SPI chipselect PMOD 3: SPI MOSI PMOD 4: SPI MISO PMOD 7: GPIO 0 PMOD 8: GPIO 1 PMOD 9: GPIO 2 PMOD 10: GPIO 3 The GPIOs are mapped at offset 48-51 of the EMIO GPIOs.
2018-06-15 11:50:34 +00:00
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_tx
Makefile: Update makefiles
2019-08-22 09:00:05 +00:00
LIB_DEPS += sysid_rom
dac_fmc_ebz: Add initial ZCU102 and ZC706 carrier support Add a generic project for the AD91xx-FMC-EBZ DAC boards connected to the ZCU102 and ZC706 carrier boards. The project is called dac_fmc_ebz as the intention is to support all DAC FMC evaluation boards with this project since they are sufficiently similar to be supported by the same design. This project will successively extended to add support for more boards. The desired DAC device and JESD operation mode must be selected from the following file: ./common/config.tcl This design can support the following FMC boards which are all pin compatible: * AD9135-FMC-EBZ * AD9136-FMC-EBZ * AD9144-FMC-EBZ * AD9152-FMC-EBZ * AD9154-FMC-EBZ * AD916x-FMC-EBZ * AD9171-FMC-EBZ * AD9172-FMC-EBZ * AD9173-FMC-EBZ Note that the AD9152-FMC-EBZ only uses the first 4 lanes, whereas all other boards use 8 lanes. This project assumes that the transceiver reference clock and SYSREF are provided via the clock distribution chip that is found on the ADxxxx-FMC-EBZ board. In terms of pin connections between the FPGA and the FMC board the AD9172-FMC-EBZ is very similar to the AD9144-FMC-EBZ. The main differences are: * The DAC txen signals are connected to different pins * The polarity of the spi_en signal is active low instead of active high * The maximum lane rate is up to 15.4 Gpbs To accommodate this 5 txctrl signals as well as the spi_en signal are connected to GPIOs. Software can decide how to use them depending on which FMC board is connected. Note that each carrier has a maximum supported lane rate. Modes of the AD9172 (and similar) that exceed the carrier specific limit can not be used on that carrier. The limits are as following: * ZC706: 10.3125 Gbps * ZCU102: 15.4 Gbps (max AD9172 lanerate) * SPI and GPIOs to PMOD header support Connect a SPI interface and some GPIOs to the PL PMOD headers on the zcu102 and zc706 carriers. This is can be used to control additional external hardware like a clock chip or an analog front-end. This is especially useful on FMC boards that do not feature a clock generator chip. The pin out is: PMOD 1: SPI clock PMOD 2: SPI chipselect PMOD 3: SPI MOSI PMOD 4: SPI MISO PMOD 7: GPIO 0 PMOD 8: GPIO 1 PMOD 9: GPIO 2 PMOD 10: GPIO 3 The GPIOs are mapped at offset 48-51 of the EMIO GPIOs.
2018-06-15 11:50:34 +00:00
LIB_DEPS += util_dacfifo
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr
include ../../scripts/project-xilinx.mk