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pluto_hdl_adi/projects/adrv9364z7020/ccbob_cmos/system_bd.tcl

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Tcl
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pzsdr1- cmos mode
2016-04-11 19:58:29 +00:00
adrv9364z7020: Rename pzsdr1 to adrv9364z7020
2017-05-25 14:20:23 +00:00
source ../common/adrv9364z7020_bd.tcl
source ../common/ccbob_bd.tcl
pzsdr1- cmos mode
2016-04-11 19:58:29 +00:00
ad9361- clkdiv to util_ad9361_divclk
2017-08-07 15:25:46 +00:00
ad_ip_parameter util_ad9361_divclk CONFIG.SEL_0_DIV 2
ad_ip_parameter util_ad9361_divclk CONFIG.SEL_1_DIV 1
pzsdr1: Added FIFOs for DAC and ADC paths so that they work at l_clk or l_clk/2
2017-01-18 10:01:24 +00:00
pzsdr1/ccbrk_cmos- updates
2016-11-17 20:32:49 +00:00
cfg_ad9361_interface CMOS
pzsdr1- cmos mode
2016-04-11 19:58:29 +00:00
ad9361- delay initialization
2017-03-15 16:06:49 +00:00
set_property CONFIG.ADC_INIT_DELAY 30 [get_bd_cells axi_ad9361]