2014-04-30 18:40:54 +00:00
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# create board design
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# interface ports
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2015-03-09 20:04:09 +00:00
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create_bd_port -dir I -type rst sys_rst
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
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create_bd_port -dir I phy_sd
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create_bd_port -dir O -type rst phy_rst_n
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sgmii_rtl:1.0 sgmii
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 phy_clk
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
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create_bd_port -dir I uart_sin
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create_bd_port -dir O uart_sout
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create_bd_port -dir O -from 7 -to 0 spi_csn_o
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create_bd_port -dir I -from 7 -to 0 spi_csn_i
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create_bd_port -dir I spi_clk_i
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create_bd_port -dir O spi_clk_o
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create_bd_port -dir I spi_sdo_i
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create_bd_port -dir O spi_sdo_o
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create_bd_port -dir I spi_sdi_i
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create_bd_port -dir I -from 31 -to 0 gpio0_i
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create_bd_port -dir O -from 31 -to 0 gpio0_o
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create_bd_port -dir O -from 31 -to 0 gpio0_t
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create_bd_port -dir I -from 31 -to 0 gpio1_i
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create_bd_port -dir O -from 31 -to 0 gpio1_o
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create_bd_port -dir O -from 31 -to 0 gpio1_t
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# interrupts
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2014-04-30 18:40:54 +00:00
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2015-03-10 20:13:32 +00:00
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create_bd_port -dir I -type intr mb_intr_05
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create_bd_port -dir I -type intr mb_intr_06
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create_bd_port -dir I -type intr mb_intr_07
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create_bd_port -dir I -type intr mb_intr_08
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create_bd_port -dir I -type intr mb_intr_12
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create_bd_port -dir I -type intr mb_intr_13
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create_bd_port -dir I -type intr mb_intr_14
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create_bd_port -dir I -type intr mb_intr_15
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2014-04-30 18:40:54 +00:00
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2015-03-09 20:04:09 +00:00
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# io settings
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2014-04-30 18:40:54 +00:00
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2015-03-09 20:04:09 +00:00
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set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst]
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set_property -dict [list CONFIG.FREQ_HZ {300000000}] [get_bd_intf_ports sys_clk]
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set_property -dict [list CONFIG.FREQ_HZ {625000000}] [get_bd_intf_ports phy_clk]
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2014-04-30 18:40:54 +00:00
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# instance: microblaze - processor
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2015-08-25 07:03:49 +00:00
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set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.5 sys_mb]
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2014-10-07 07:17:24 +00:00
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set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb
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2014-12-04 08:47:02 +00:00
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set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
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2014-04-30 18:40:54 +00:00
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# instance: microblaze - local memory & bus
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set sys_dlmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_dlmb]
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set sys_ilmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_ilmb]
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set sys_dlmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_dlmb_cntlr]
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set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
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set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
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set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
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2016-03-18 13:22:42 +00:00
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set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram]
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2014-04-30 18:40:54 +00:00
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set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
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# instance: microblaze- mdm
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2015-01-13 18:39:03 +00:00
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set sys_mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 sys_mb_debug]
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2014-04-30 18:40:54 +00:00
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set_property -dict [list CONFIG.C_USE_UART {1}] $sys_mb_debug
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2014-07-23 20:25:17 +00:00
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# instance: system reset/clocks
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set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
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2014-04-30 18:40:54 +00:00
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# instance: ddr (mig)
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2016-05-27 11:59:28 +00:00
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set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:1.1 axi_ddr_cntrl]
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2014-04-30 18:40:54 +00:00
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source $ad_hdl_dir/projects/common/kcu105/kcu105_system_mig.tcl
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2014-07-29 13:15:30 +00:00
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set axi_ddr_cntrl_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ddr_cntrl_rstgen]
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2014-04-30 18:40:54 +00:00
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# instance: default peripherals
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2016-05-27 11:59:28 +00:00
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set axi_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 axi_ethernet_clkgen]
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2014-07-29 13:15:30 +00:00
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set_property -dict [list CONFIG.PRIM_IN_FREQ {625}] $axi_ethernet_clkgen
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set_property -dict [list CONFIG.PRIM_SOURCE {Differential_clock_capable_pin}] $axi_ethernet_clkgen
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set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125}] $axi_ethernet_clkgen
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set_property -dict [list CONFIG.CLKOUT2_USED {true}] $axi_ethernet_clkgen
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set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {312}] $axi_ethernet_clkgen
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set_property -dict [list CONFIG.CLKOUT3_USED {true}] $axi_ethernet_clkgen
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set_property -dict [list CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {625}] $axi_ethernet_clkgen
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set_property -dict [list CONFIG.CLKOUT4_USED {false}] $axi_ethernet_clkgen
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set_property -dict [list CONFIG.USE_LOCKED {true}] $axi_ethernet_clkgen
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set_property -dict [list CONFIG.USE_RESET {false}] $axi_ethernet_clkgen
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set axi_ethernet_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ethernet_rstgen]
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2016-02-26 18:19:49 +00:00
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set axi_ethernet_idelayctrl [create_bd_cell -type ip -vlnv xilinx.com:ip:util_idelay_ctrl:1.0 axi_ethernet_idelayctrl]
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2014-07-29 13:15:30 +00:00
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2015-08-25 07:03:49 +00:00
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set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.0 axi_ethernet]
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2014-04-30 18:40:54 +00:00
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set_property -dict [list CONFIG.PHY_TYPE {SGMII}] $axi_ethernet
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2014-05-06 19:38:44 +00:00
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set_property -dict [list CONFIG.ENABLE_LVDS {true}] $axi_ethernet
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2014-12-05 13:48:37 +00:00
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set_property -dict [list CONFIG.SupportLevel {0}] $axi_ethernet
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2014-12-04 08:49:09 +00:00
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set_property -dict [list CONFIG.TXCSUM {Full}] $axi_ethernet
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set_property -dict [list CONFIG.RXCSUM {Full}] $axi_ethernet
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set_property -dict [list CONFIG.TXMEM {8k}] $axi_ethernet
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set_property -dict [list CONFIG.RXMEM {8k}] $axi_ethernet
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2014-04-30 18:40:54 +00:00
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set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma]
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set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma
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set_property -dict [list CONFIG.c_sg_use_stsapp_length {1}] $axi_ethernet_dma
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set_property -dict [list CONFIG.c_include_s2mm_dre {1}] $axi_ethernet_dma
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set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
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set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart]
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set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart
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set axi_timer [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer]
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2015-03-09 20:04:09 +00:00
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set axi_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_spi]
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set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_spi
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set_property -dict [list CONFIG.C_NUM_SS_BITS {8}] $axi_spi
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set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_spi
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2014-04-30 18:40:54 +00:00
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2015-03-09 20:04:09 +00:00
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set axi_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio]
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set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio
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2015-08-25 07:07:11 +00:00
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set_property -dict [list CONFIG.C_GPIO_WIDTH {32}] $axi_gpio
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2015-03-09 20:04:09 +00:00
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set_property -dict [list CONFIG.C_GPIO2_WIDTH {32}] $axi_gpio
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set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio
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2014-04-30 18:40:54 +00:00
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# instance: interrupt
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set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc]
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set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc
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2014-10-28 19:51:19 +00:00
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set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
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2015-03-09 20:04:09 +00:00
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set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
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2014-10-28 19:51:19 +00:00
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2014-07-23 20:25:17 +00:00
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# connections
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2014-04-30 18:40:54 +00:00
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2015-03-05 15:54:46 +00:00
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ad_connect sys_mb_debug/Debug_SYS_Rst sys_rstgen/mb_debug_sys_rst
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ad_connect sys_rstgen/mb_reset sys_mb/Reset
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ad_connect sys_rstgen/bus_struct_reset sys_dlmb/SYS_Rst
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ad_connect sys_rstgen/bus_struct_reset sys_ilmb/SYS_Rst
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ad_connect sys_rstgen/bus_struct_reset sys_dlmb_cntlr/LMB_Rst
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ad_connect sys_rstgen/bus_struct_reset sys_ilmb_cntlr/LMB_Rst
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2014-04-30 18:40:54 +00:00
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# microblaze local memory
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2015-03-05 15:54:46 +00:00
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ad_connect sys_mb/DLMB sys_dlmb/LMB_M
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ad_connect sys_mb/ILMB sys_ilmb/LMB_M
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ad_connect sys_dlmb/LMB_Sl_0 sys_dlmb_cntlr/SLMB
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ad_connect sys_ilmb/LMB_Sl_0 sys_ilmb_cntlr/SLMB
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ad_connect sys_dlmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTA
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ad_connect sys_ilmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTB
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2014-04-30 18:40:54 +00:00
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# microblaze debug & interrupt
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2015-03-05 15:54:46 +00:00
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ad_connect sys_mb_debug/MBDEBUG_0 sys_mb/DEBUG
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ad_connect axi_intc/interrupt sys_mb/INTERRUPT
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2015-08-25 06:58:32 +00:00
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ad_connect axi_intc/intr sys_concat_intc/dout
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2014-04-30 18:40:54 +00:00
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# defaults (peripherals)
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2015-03-06 17:37:31 +00:00
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ad_connect sys_mem_clk axi_ddr_cntrl/c0_ddr4_ui_clk
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2015-03-05 15:54:46 +00:00
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ad_connect sys_cpu_clk axi_ddr_cntrl/addn_ui_clkout1
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ad_connect sys_200m_clk axi_ddr_cntrl/addn_ui_clkout2
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ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
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ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
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ad_connect sys_mem_resetn axi_ddr_cntrl_rstgen/peripheral_aresetn
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2015-03-06 17:37:31 +00:00
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ad_connect sys_mem_resetn axi_ddr_cntrl/c0_ddr4_aresetn
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2014-04-30 18:40:54 +00:00
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2015-03-05 15:54:46 +00:00
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ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
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ad_connect sys_cpu_clk sys_mb/Clk
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ad_connect sys_cpu_clk sys_dlmb/LMB_Clk
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ad_connect sys_cpu_clk sys_ilmb/LMB_Clk
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ad_connect sys_cpu_clk sys_dlmb_cntlr/LMB_Clk
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ad_connect sys_cpu_clk sys_ilmb_cntlr/LMB_Clk
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2015-08-25 06:58:32 +00:00
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ad_connect sys_cpu_clk axi_ethernet/axis_clk
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2014-04-30 18:40:54 +00:00
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# defaults (interrupts)
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2015-03-05 15:54:46 +00:00
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ad_connect sys_concat_intc/In0 axi_timer/interrupt
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ad_connect sys_concat_intc/In1 axi_ethernet/interrupt
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ad_connect sys_concat_intc/In2 axi_ethernet_dma/mm2s_introut
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ad_connect sys_concat_intc/In3 axi_ethernet_dma/s2mm_introut
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ad_connect sys_concat_intc/In4 axi_uart/interrupt
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2015-03-09 20:04:09 +00:00
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ad_connect sys_concat_intc/In5 mb_intr_05
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ad_connect sys_concat_intc/In6 mb_intr_06
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2015-03-10 20:13:32 +00:00
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ad_connect sys_concat_intc/In7 mb_intr_07
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ad_connect sys_concat_intc/In8 mb_intr_08
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2015-03-05 15:54:46 +00:00
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ad_connect sys_concat_intc/In9 axi_iic_main/iic2intc_irpt
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2015-03-09 20:04:09 +00:00
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ad_connect sys_concat_intc/In10 axi_spi/ip2intc_irpt
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ad_connect sys_concat_intc/In11 axi_gpio/ip2intc_irpt
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ad_connect sys_concat_intc/In12 mb_intr_12
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ad_connect sys_concat_intc/In13 mb_intr_13
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ad_connect sys_concat_intc/In14 mb_intr_14
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ad_connect sys_concat_intc/In15 mb_intr_15
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2014-04-30 18:40:54 +00:00
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2014-07-29 13:15:30 +00:00
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# defaults (ddr)
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2015-03-05 15:54:46 +00:00
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ad_connect sys_rst axi_ddr_cntrl/sys_rst
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2015-03-09 20:04:09 +00:00
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ad_connect c0_ddr4 axi_ddr_cntrl/C0_DDR4
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ad_connect sys_clk axi_ddr_cntrl/C0_SYS_CLK
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2014-07-29 13:15:30 +00:00
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2015-03-05 15:54:46 +00:00
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ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_rstgen/ext_reset_in
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ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ethernet_rstgen/ext_reset_in
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ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ddr_cntrl_rstgen/ext_reset_in
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ad_connect sys_mem_clk axi_ddr_cntrl_rstgen/slowest_sync_clk
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2014-07-29 13:15:30 +00:00
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# defaults (ethernet)
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2015-03-05 15:54:46 +00:00
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ad_connect phy_clk axi_ethernet_clkgen/CLK_IN1_D
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ad_connect mdio axi_ethernet/mdio
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ad_connect sgmii axi_ethernet/sgmii
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ad_connect axi_ethernet/s_axis_txd axi_ethernet_dma/M_AXIS_MM2S
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ad_connect axi_ethernet/s_axis_txc axi_ethernet_dma/M_AXIS_CNTRL
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ad_connect axi_ethernet/m_axis_rxd axi_ethernet_dma/S_AXIS_S2MM
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ad_connect axi_ethernet/m_axis_rxs axi_ethernet_dma/S_AXIS_STS
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ad_connect phy_sd axi_ethernet/signal_detect
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2015-08-25 06:58:32 +00:00
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ad_connect sys_cpu_resetn phy_rst_n
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2015-03-05 15:54:46 +00:00
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ad_connect axi_ethernet_clkgen/clk_out1 axi_ethernet/clk125m
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ad_connect axi_ethernet_clkgen/clk_out1 axi_ethernet_rstgen/slowest_sync_clk
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ad_connect axi_ethernet_clkgen/clk_out2 axi_ethernet/clk312
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ad_connect axi_ethernet_clkgen/clk_out3 axi_ethernet/clk625
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ad_connect axi_ethernet_clkgen/locked axi_ethernet/mmcm_locked
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ad_connect axi_ethernet_rstgen/peripheral_reset axi_ethernet/rst_125
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ad_connect axi_ethernet/axi_txd_arstn axi_ethernet_dma/mm2s_prmry_reset_out_n
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ad_connect axi_ethernet/axi_txc_arstn axi_ethernet_dma/mm2s_cntrl_reset_out_n
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ad_connect axi_ethernet/axi_rxd_arstn axi_ethernet_dma/s2mm_prmry_reset_out_n
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ad_connect axi_ethernet/axi_rxs_arstn axi_ethernet_dma/s2mm_sts_reset_out_n
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2016-02-26 18:19:49 +00:00
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ad_connect axi_ethernet_idelayctrl/rdy axi_ethernet/idelay_rdy_in
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ad_connect axi_ethernet_idelayctrl/rst axi_ethernet_rstgen/peripheral_reset
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ad_connect axi_ethernet_idelayctrl/ref_clk axi_ethernet_clkgen/clk_out3
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2014-07-29 13:15:30 +00:00
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# defaults (misc)
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2015-03-05 15:54:46 +00:00
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ad_connect iic_main axi_iic_main/iic
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ad_connect uart_sin axi_uart/rx
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ad_connect uart_sout axi_uart/tx
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2015-03-09 20:04:09 +00:00
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ad_connect spi_csn_i axi_spi/ss_i
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ad_connect spi_csn_o axi_spi/ss_o
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ad_connect spi_clk_i axi_spi/sck_i
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ad_connect spi_clk_o axi_spi/sck_o
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ad_connect spi_sdo_i axi_spi/io0_i
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ad_connect spi_sdo_o axi_spi/io0_o
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ad_connect spi_sdi_i axi_spi/io1_i
|
2015-08-25 06:58:32 +00:00
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ad_connect gpio0_i axi_gpio/gpio_io_i
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ad_connect gpio0_o axi_gpio/gpio_io_o
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ad_connect gpio0_t axi_gpio/gpio_io_t
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ad_connect gpio1_i axi_gpio/gpio2_io_i
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ad_connect gpio1_o axi_gpio/gpio2_io_o
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ad_connect gpio1_t axi_gpio/gpio2_io_t
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ad_connect sys_cpu_clk axi_spi/ext_spi_clk
|
2014-04-30 18:40:54 +00:00
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2015-03-05 15:54:46 +00:00
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# defaults (interconnect - processor)
|
2014-04-30 18:40:54 +00:00
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2015-03-05 15:54:46 +00:00
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ad_cpu_interconnect 0x41400000 sys_mb_debug
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ad_cpu_interconnect 0x40E00000 axi_ethernet
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ad_cpu_interconnect 0x41E10000 axi_ethernet_dma
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ad_cpu_interconnect 0x40600000 axi_uart
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ad_cpu_interconnect 0x41C00000 axi_timer
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ad_cpu_interconnect 0x41200000 axi_intc
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ad_cpu_interconnect 0x41600000 axi_iic_main
|
2015-03-09 20:04:09 +00:00
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ad_cpu_interconnect 0x40000000 axi_gpio
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ad_cpu_interconnect 0x44A70000 axi_spi
|
2015-03-05 15:54:46 +00:00
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|
2015-03-06 17:37:31 +00:00
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create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ddr_interconnect
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set_property CONFIG.NUM_MI {1} [get_bd_cells axi_ddr_interconnect]
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set_property CONFIG.NUM_SI {1} [get_bd_cells axi_ddr_interconnect]
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ad_connect axi_ddr_interconnect/M00_AXI axi_ddr_cntrl/C0_DDR4_S_AXI
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ad_connect sys_mem_clk axi_ddr_interconnect/ACLK
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ad_connect sys_mem_clk axi_ddr_interconnect/M00_ACLK
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ad_connect sys_mem_resetn axi_ddr_interconnect/ARESETN
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ad_connect sys_mem_resetn axi_ddr_interconnect/M00_ARESETN
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ad_connect sys_cpu_resetn axi_ddr_interconnect/S00_ARESETN
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ad_mem_hp0_interconnect sys_cpu_clk axi_ddr_interconnect/S00_AXI
|
2015-03-05 15:54:46 +00:00
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ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_DC
|
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ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_IC
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ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_SG
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ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_MM2S
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ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_S2MM
|
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|
2015-03-09 20:04:09 +00:00
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|
create_bd_addr_seg -range 0x20000 -offset 0x0 [get_bd_addr_spaces sys_mb/Data] \
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|
|
[get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_dlmb_cntlr
|
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|
create_bd_addr_seg -range 0x20000 -offset 0x0 [get_bd_addr_spaces sys_mb/Instruction] \
|
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|
|
[get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_ilmb_cntlr
|
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2014-04-30 18:40:54 +00:00
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