282 lines
8.4 KiB
Coq
282 lines
8.4 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// dac vdma read
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module ad_axis_dma_tx (
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// vdma interface
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dma_clk,
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dma_rst,
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dma_fs,
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dma_valid,
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dma_data,
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dma_ready,
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dma_ovf,
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dma_unf,
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// dac interface
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dac_clk,
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dac_rst,
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dac_rd,
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dac_valid,
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dac_data,
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// processor interface
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dma_frmcnt);
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// parameters
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parameter DATA_WIDTH = 64;
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localparam DW = DATA_WIDTH - 1;
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localparam BUF_THRESHOLD_LO = 6'd3;
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localparam BUF_THRESHOLD_HI = 6'd60;
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localparam RDY_THRESHOLD_LO = 6'd40;
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localparam RDY_THRESHOLD_HI = 6'd50;
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// vdma interface
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input dma_clk;
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input dma_rst;
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output dma_fs;
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input dma_valid;
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input [DW:0] dma_data;
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output dma_ready;
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output dma_ovf;
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output dma_unf;
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// dac interface
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input dac_clk;
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input dac_rst;
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input dac_rd;
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output dac_valid;
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output [DW:0] dac_data;
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// processor interface
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input [31:0] dma_frmcnt;
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// internal registers
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reg dac_start_m1 = 'd0;
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reg dac_start = 'd0;
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reg dac_resync_m1 = 'd0;
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reg dac_resync = 'd0;
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reg [ 5:0] dac_raddr = 'd0;
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reg [ 5:0] dac_raddr_g = 'd0;
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reg dac_rd_d = 'd0;
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reg dac_rd_2d = 'd0;
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reg dac_valid = 'd0;
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reg [DW:0] dac_data = 'd0;
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reg [31:0] dma_clkcnt = 'd0;
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reg dma_fs = 'd0;
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reg [ 5:0] dma_raddr_g_m1 = 'd0;
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reg [ 5:0] dma_raddr_g_m2 = 'd0;
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reg [ 5:0] dma_raddr = 'd0;
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reg [ 5:0] dma_addr_diff = 'd0;
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reg dma_ready = 'd0;
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reg dma_almost_full = 'd0;
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reg dma_almost_empty = 'd0;
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reg dma_ovf = 'd0;
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reg dma_unf = 'd0;
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reg dma_resync = 'd0;
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reg dma_start = 'd0;
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reg dma_wr = 'd0;
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reg [ 5:0] dma_waddr = 'd0;
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reg [DW:0] dma_wdata = 'd0;
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// internal signals
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wire dma_wr_s;
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wire [ 6:0] dma_addr_diff_s;
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wire dma_ovf_s;
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wire dma_unf_s;
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wire [DW:0] dac_rdata_s;
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// binary to grey coversion
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function [7:0] b2g;
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input [7:0] b;
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reg [7:0] g;
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begin
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g[7] = b[7];
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g[6] = b[7] ^ b[6];
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g[5] = b[6] ^ b[5];
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g[4] = b[5] ^ b[4];
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g[3] = b[4] ^ b[3];
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g[2] = b[3] ^ b[2];
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g[1] = b[2] ^ b[1];
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g[0] = b[1] ^ b[0];
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b2g = g;
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end
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endfunction
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// grey to binary conversion
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function [7:0] g2b;
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input [7:0] g;
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reg [7:0] b;
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begin
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b[7] = g[7];
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b[6] = b[7] ^ g[6];
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b[5] = b[6] ^ g[5];
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b[4] = b[5] ^ g[4];
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b[3] = b[4] ^ g[3];
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b[2] = b[3] ^ g[2];
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b[1] = b[2] ^ g[1];
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b[0] = b[1] ^ g[0];
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g2b = b;
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end
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endfunction
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// dac read interface
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always @(posedge dac_clk) begin
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if (dac_rst == 1'b1) begin
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dac_start_m1 <= 'd0;
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dac_start <= 'd0;
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dac_resync_m1 <= 'd0;
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dac_resync <= 'd0;
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end else begin
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dac_start_m1 <= dma_start;
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dac_start <= dac_start_m1;
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dac_resync_m1 <= dma_resync;
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dac_resync <= dac_resync_m1;
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end
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if ((dac_start == 1'b0) || (dac_resync == 1'b1) || (dac_rst == 1'b1)) begin
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dac_raddr <= 6'd0;
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end else if (dac_rd == 1'b1) begin
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dac_raddr <= dac_raddr + 1'b1;
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end
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dac_raddr_g <= b2g(dac_raddr);
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dac_rd_d <= dac_rd;
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dac_rd_2d <= dac_rd_d;
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dac_valid <= dac_rd_2d;
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dac_data <= dac_rdata_s;
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end
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// generate fsync
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always @(posedge dma_clk) begin
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if ((dma_resync == 1'b1) || (dma_rst == 1'b1) || (dma_clkcnt >= dma_frmcnt)) begin
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dma_clkcnt <= 16'd0;
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end else begin
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dma_clkcnt <= dma_clkcnt + 1'b1;
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end
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if (dma_clkcnt == 32'd1) begin
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dma_fs <= 1'b1;
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end else begin
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dma_fs <= 1'b0;
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end
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end
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// overflow or underflow status
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assign dma_addr_diff_s = {1'b1, dma_waddr} - dma_raddr;
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assign dma_ovf_s = (dma_addr_diff < BUF_THRESHOLD_LO) ? dma_almost_full : 1'b0;
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assign dma_unf_s = (dma_addr_diff > BUF_THRESHOLD_HI) ? dma_almost_empty : 1'b0;
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always @(posedge dma_clk) begin
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if (dma_rst == 1'b1) begin
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dma_raddr_g_m1 <= 'd0;
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dma_raddr_g_m2 <= 'd0;
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end else begin
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dma_raddr_g_m1 <= dac_raddr_g;
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dma_raddr_g_m2 <= dma_raddr_g_m1;
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end
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dma_raddr <= g2b(dma_raddr_g_m2);
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dma_addr_diff <= dma_addr_diff_s[5:0];
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if (dma_addr_diff >= RDY_THRESHOLD_HI) begin
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dma_ready <= 1'b0;
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end else if (dma_addr_diff <= RDY_THRESHOLD_LO) begin
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dma_ready <= 1'b1;
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end
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if (dma_addr_diff > BUF_THRESHOLD_HI) begin
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dma_almost_full <= 1'b1;
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end else begin
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dma_almost_full <= 1'b0;
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end
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if (dma_addr_diff < BUF_THRESHOLD_LO) begin
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dma_almost_empty <= 1'b1;
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end else begin
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dma_almost_empty <= 1'b0;
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end
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dma_ovf <= dma_ovf_s;
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dma_unf <= dma_unf_s;
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dma_resync <= dma_ovf | dma_unf;
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end
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// vdma write
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assign dma_wr_s = dma_valid & dma_ready;
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always @(posedge dma_clk) begin
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if (dma_rst == 1'b1) begin
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dma_start <= 1'b0;
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end else if (dma_wr_s == 1'b1) begin
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dma_start <= 1'b1;
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end
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dma_wr <= dma_wr_s;
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if ((dma_resync == 1'b1) || (dma_rst == 1'b1)) begin
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dma_waddr <= 6'd0;
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end else if (dma_wr == 1'b1) begin
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dma_waddr <= dma_waddr + 1'b1;
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end
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dma_wdata <= dma_data;
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end
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// memory
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ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(6)) i_mem (
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.clka (dma_clk),
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.wea (dma_wr),
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.addra (dma_waddr),
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.dina (dma_wdata),
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.clkb (dac_clk),
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.addrb (dac_raddr),
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.doutb (dac_rdata_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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