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# device settings
set_global_assignment - name FAMILY " A r r i a V "
set_global_assignment - name DEVICE 5 ASTFD5K3F40I3ES
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# i2c (fmc)
set_location_assignment PIN_F26 - to fmca_scl
set_location_assignment PIN_G26 - to fmca_sda
set_instance_assignment - name IO_STANDARD " 2 . 5 V " - to fmca_scl
set_instance_assignment - name IO_STANDARD " 2 . 5 V " - to fmca_sda
set_instance_assignment - name WEAK_PULL_UP_RESISTOR ON - to fmca_scl
set_instance_assignment - name WEAK_PULL_UP_RESISTOR ON - to fmca_sda
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# led & switches
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set_location_assignment PIN_AH24 - to gpio_bd_o[ 0 ] ; # # led[0]
set_location_assignment PIN_AU24 - to gpio_bd_o[ 1 ] ; # # led[1]
set_location_assignment PIN_AT24 - to gpio_bd_o[ 2 ] ; # # led[2]
set_location_assignment PIN_AD24 - to gpio_bd_o[ 3 ] ; # # led[3]
set_location_assignment PIN_AT23 - to gpio_bd_i[ 0 ] ; # # push_buttons[0]
set_location_assignment PIN_AP24 - to gpio_bd_i[ 1 ] ; # # push_buttons[1]
set_location_assignment PIN_AW24 - to gpio_bd_i[ 2 ] ; # # push_buttons[2]
set_location_assignment PIN_AW23 - to gpio_bd_i[ 3 ] ; # # push_buttons[3]
set_location_assignment PIN_AL24 - to gpio_bd_i[ 4 ] ; # # dip_switches[0]
set_location_assignment PIN_AF24 - to gpio_bd_i[ 5 ] ; # # dip_switches[1]
set_location_assignment PIN_AE24 - to gpio_bd_i[ 6 ] ; # # dip_switches[2]
set_location_assignment PIN_AU23 - to gpio_bd_i[ 7 ] ; # # dip_switches[3]
set_instance_assignment - name IO_STANDARD " 1 . 5 V " - to gpio_bd_o[ 0 ]
set_instance_assignment - name IO_STANDARD " 1 . 5 V " - to gpio_bd_o[ 1 ]
set_instance_assignment - name IO_STANDARD " 1 . 5 V " - to gpio_bd_o[ 2 ]
set_instance_assignment - name IO_STANDARD " 1 . 5 V " - to gpio_bd_o[ 3 ]
set_instance_assignment - name IO_STANDARD " 1 . 5 V " - to gpio_bd_i[ 0 ]
set_instance_assignment - name IO_STANDARD " 1 . 5 V " - to gpio_bd_i[ 1 ]
set_instance_assignment - name IO_STANDARD " 1 . 5 V " - to gpio_bd_i[ 2 ]
set_instance_assignment - name IO_STANDARD " 1 . 5 V " - to gpio_bd_i[ 3 ]
set_instance_assignment - name IO_STANDARD " 1 . 5 V " - to gpio_bd_i[ 4 ]
set_instance_assignment - name IO_STANDARD " 1 . 5 V " - to gpio_bd_i[ 5 ]
set_instance_assignment - name IO_STANDARD " 1 . 5 V " - to gpio_bd_i[ 6 ]
set_instance_assignment - name IO_STANDARD " 1 . 5 V " - to gpio_bd_i[ 7 ]
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# uart
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set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to uart0_rx
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to uart0_tx
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# usb
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_clk
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_stp
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_dir
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_nxt
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d0
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d1
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d2
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d3
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d4
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d5
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d6
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d7
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# sdio
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set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to sdio_clk
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to sdio_cmd
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to sdio_d0
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to sdio_d1
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to sdio_d2
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to sdio_d3
# qspi
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to qspi_ss0
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to qspi_clk
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to qspi_io0
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to qspi_io1
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to qspi_io2
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to qspi_io3
# ethernet
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_tx_clk
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_tx_ctl
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_txd0
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_txd1
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_txd2
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_txd3
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_rx_clk
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_rx_ctl
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_rxd0
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_rxd1
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_rxd2
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_rxd3
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_mdc
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_mdio
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# ddr
set_instance_assignment - name D5_DELAY 2 - to ddr3_ck_p
set_instance_assignment - name D5_DELAY 2 - to ddr3_ck_n
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 0 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 1 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 2 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 3 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 4 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 5 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 6 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 7 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 8 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 9 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 10 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 11 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 12 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 13 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 14 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_ba[ 0 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_ba[ 1 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_ba[ 2 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_cas_n
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_cke
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_cs_n
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_odt
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_ras_n
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_reset_n
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_we_n
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uio_pads| dq_ddio[ 0 ] .read_capture_clk_buffer
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uio_pads| dq_ddio[ 1 ] .read_capture_clk_buffer
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uio_pads| dq_ddio[ 2 ] .read_capture_clk_buffer
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uio_pads| dq_ddio[ 3 ] .read_capture_clk_buffer
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uio_pads| dq_ddio[ 4 ] .read_capture_clk_buffer
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_wraddress[ 0 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_wraddress[ 1 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_wraddress[ 2 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_wraddress[ 3 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_wraddress[ 4 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_write_side[ 0 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_write_side[ 1 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_write_side[ 2 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_write_side[ 3 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_write_side[ 4 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| ureset| phy_reset_mem_stable_n
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| ureset| phy_reset_n
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 0 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 1 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 2 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 3 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 4 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 5 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 6 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 7 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 8 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 9 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 10 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 11 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 12 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 13 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 14 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 15 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 16 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 17 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 18 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 19 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 20 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 21 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 22 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 23 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 24 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 25 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 26 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 27 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 28 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 29 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 30 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 31 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 32 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 33 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 34 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 35 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 36 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 37 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 38 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 39 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 0 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 1 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 2 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 3 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 4 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 0 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 1 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 2 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 3 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 4 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_ck_p
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_ck_n
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_p[ 0 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_p[ 1 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_p[ 2 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_p[ 3 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_p[ 4 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_n[ 0 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_n[ 1 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_n[ 2 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_n[ 3 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_n[ 4 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 0 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 1 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 2 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 3 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 4 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 5 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 6 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 7 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 8 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 9 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 10 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 11 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 12 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 13 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 14 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_ba[ 0 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_ba[ 1 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_ba[ 2 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_cas_n
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_cke
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_cs_n
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dm[ 0 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dm[ 1 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dm[ 2 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dm[ 3 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dm[ 4 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 0 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 1 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 2 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 3 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 4 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 5 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 6 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 7 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 8 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 9 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 10 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 11 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 12 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 13 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 14 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 15 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 16 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 17 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 18 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 19 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 20 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 21 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 22 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 23 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 24 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 25 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 26 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 27 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 28 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 29 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 30 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 31 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 32 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 33 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 34 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 35 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 36 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 37 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 38 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 39 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_odt
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_ras_n
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_reset_n
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_we_n
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_oct_rzqin
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dm[ 0 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dm[ 1 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dm[ 2 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dm[ 3 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dm[ 4 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 0 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 1 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 2 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 3 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 4 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 5 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 6 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 7 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 8 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 9 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 10 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 11 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 12 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 13 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 14 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 15 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 16 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 17 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 18 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 19 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 20 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 21 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 22 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 23 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 24 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 25 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 26 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 27 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 28 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 29 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 30 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 31 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 32 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 33 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 34 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 35 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 36 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 37 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 38 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 39 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 0 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 1 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 2 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 3 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 4 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 0 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 1 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 2 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 3 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 4 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H O U T C A L I B R A T I O N " - to ddr3_ck_p
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H O U T C A L I B R A T I O N " - to ddr3_ck_n
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 0 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 1 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 2 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 3 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 4 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 5 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 6 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 7 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 8 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 9 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 10 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 11 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 12 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 13 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 14 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_ba[ 0 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_ba[ 1 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_ba[ 2 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_cas_n
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_ck_p
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_ck_n
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_cke
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_cs_n
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dm[ 0 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dm[ 1 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dm[ 2 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dm[ 3 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dm[ 4 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 0 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 1 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 2 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 3 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 4 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 5 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 6 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 7 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 8 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 9 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 10 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 11 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 12 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 13 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 14 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 15 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 16 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 17 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 18 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 19 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 20 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 21 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 22 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 23 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 24 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 25 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 26 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 27 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 28 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 29 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 30 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 31 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 32 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 33 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 34 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 35 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 36 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 37 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 38 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 39 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_p[ 0 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_p[ 1 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_p[ 2 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_p[ 3 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_p[ 4 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_n[ 0 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_n[ 1 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_n[ 2 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_n[ 3 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_n[ 4 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_odt
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_ras_n
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_reset_n
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_we_n
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set_location_assignment PIN_A11 - to ddr3_ck_p
set_location_assignment PIN_B10 - to ddr3_ck_n
set_location_assignment PIN_N9 - to ddr3_a[ 0 ]
set_location_assignment PIN_M9 - to ddr3_a[ 1 ]
set_location_assignment PIN_N10 - to ddr3_a[ 2 ]
set_location_assignment PIN_M10 - to ddr3_a[ 3 ]
set_location_assignment PIN_A8 - to ddr3_a[ 4 ]
set_location_assignment PIN_B7 - to ddr3_a[ 5 ]
set_location_assignment PIN_B9 - to ddr3_a[ 6 ]
set_location_assignment PIN_A9 - to ddr3_a[ 7 ]
set_location_assignment PIN_D9 - to ddr3_a[ 8 ]
set_location_assignment PIN_C10 - to ddr3_a[ 9 ]
set_location_assignment PIN_K7 - to ddr3_a[ 10 ]
set_location_assignment PIN_J7 - to ddr3_a[ 11 ]
set_location_assignment PIN_F9 - to ddr3_a[ 12 ]
set_location_assignment PIN_E9 - to ddr3_a[ 13 ]
set_location_assignment PIN_D11 - to ddr3_a[ 14 ]
set_location_assignment PIN_L7 - to ddr3_ba[ 0 ]
set_location_assignment PIN_C9 - to ddr3_ba[ 1 ]
set_location_assignment PIN_D8 - to ddr3_ba[ 2 ]
set_location_assignment PIN_G9 - to ddr3_cas_n
set_location_assignment PIN_R8 - to ddr3_cke
set_location_assignment PIN_H9 - to ddr3_cs_n
set_location_assignment PIN_H7 - to ddr3_odt
set_location_assignment PIN_G8 - to ddr3_ras_n
set_location_assignment PIN_E3 - to ddr3_reset_n
set_location_assignment PIN_J8 - to ddr3_we_n
set_location_assignment PIN_C6 - to ddr3_dm[ 0 ]
set_location_assignment PIN_E4 - to ddr3_dm[ 1 ]
set_location_assignment PIN_D3 - to ddr3_dm[ 2 ]
set_location_assignment PIN_D1 - to ddr3_dm[ 3 ]
set_location_assignment PIN_T7 - to ddr3_dm[ 4 ]
set_location_assignment PIN_D7 - to ddr3_dq[ 0 ]
set_location_assignment PIN_C7 - to ddr3_dq[ 1 ]
set_location_assignment PIN_R10 - to ddr3_dq[ 2 ]
set_location_assignment PIN_G7 - to ddr3_dq[ 3 ]
set_location_assignment PIN_A6 - to ddr3_dq[ 4 ]
set_location_assignment PIN_A7 - to ddr3_dq[ 5 ]
set_location_assignment PIN_L6 - to ddr3_dq[ 6 ]
set_location_assignment PIN_D6 - to ddr3_dq[ 7 ]
set_location_assignment PIN_H6 - to ddr3_dq[ 8 ]
set_location_assignment PIN_G6 - to ddr3_dq[ 9 ]
set_location_assignment PIN_N8 - to ddr3_dq[ 10 ]
set_location_assignment PIN_G5 - to ddr3_dq[ 11 ]
set_location_assignment PIN_A4 - to ddr3_dq[ 12 ]
set_location_assignment PIN_A5 - to ddr3_dq[ 13 ]
set_location_assignment PIN_R9 - to ddr3_dq[ 14 ]
set_location_assignment PIN_F4 - to ddr3_dq[ 15 ]
set_location_assignment PIN_J5 - to ddr3_dq[ 16 ]
set_location_assignment PIN_K5 - to ddr3_dq[ 17 ]
set_location_assignment PIN_N7 - to ddr3_dq[ 18 ]
set_location_assignment PIN_F3 - to ddr3_dq[ 19 ]
set_location_assignment PIN_H3 - to ddr3_dq[ 20 ]
set_location_assignment PIN_J4 - to ddr3_dq[ 21 ]
set_location_assignment PIN_M5 - to ddr3_dq[ 22 ]
set_location_assignment PIN_C3 - to ddr3_dq[ 23 ]
set_location_assignment PIN_A2 - to ddr3_dq[ 24 ]
set_location_assignment PIN_A3 - to ddr3_dq[ 25 ]
set_location_assignment PIN_P7 - to ddr3_dq[ 26 ]
set_location_assignment PIN_C1 - to ddr3_dq[ 27 ]
set_location_assignment PIN_G2 - to ddr3_dq[ 28 ]
set_location_assignment PIN_F2 - to ddr3_dq[ 29 ]
set_location_assignment PIN_M3 - to ddr3_dq[ 30 ]
set_location_assignment PIN_E1 - to ddr3_dq[ 31 ]
set_location_assignment PIN_G1 - to ddr3_dq[ 32 ]
set_location_assignment PIN_F1 - to ddr3_dq[ 33 ]
set_location_assignment PIN_P6 - to ddr3_dq[ 34 ]
set_location_assignment PIN_L1 - to ddr3_dq[ 35 ]
set_location_assignment PIN_M2 - to ddr3_dq[ 36 ]
set_location_assignment PIN_M1 - to ddr3_dq[ 37 ]
set_location_assignment PIN_N1 - to ddr3_dq[ 38 ]
set_location_assignment PIN_R6 - to ddr3_dq[ 39 ]
set_location_assignment PIN_E7 - to ddr3_dqs_n[ 0 ]
set_location_assignment PIN_E6 - to ddr3_dqs_n[ 1 ]
set_location_assignment PIN_H4 - to ddr3_dqs_n[ 2 ]
set_location_assignment PIN_D2 - to ddr3_dqs_n[ 3 ]
set_location_assignment PIN_H1 - to ddr3_dqs_n[ 4 ]
set_location_assignment PIN_F7 - to ddr3_dqs_p[ 0 ]
set_location_assignment PIN_D5 - to ddr3_dqs_p[ 1 ]
set_location_assignment PIN_G4 - to ddr3_dqs_p[ 2 ]
set_location_assignment PIN_C2 - to ddr3_dqs_p[ 3 ]
set_location_assignment PIN_J1 - to ddr3_dqs_p[ 4 ]
set_location_assignment PIN_K9 - to ddr3_oct_rzqin
2014-04-28 15:02:40 +00:00
set_instance_assignment - name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst
set_instance_assignment - name PLL_COMPENSATION_MODE DIRECT - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| pll0| fbout
# globals
set_global_assignment - name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON
set_global_assignment - name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
set_global_assignment - name OPTIMIZE_MULTI_CORNER_TIMING ON
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set_global_assignment - name OPTIMIZE_HOLD_TIMING " A L L P A T H S "
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set_global_assignment - name ECO_REGENERATE_REPORT ON
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set_global_assignment - name STRATIX_DEVICE_IO_STANDARD " 2 . 5 V "
2014-04-28 15:02:40 +00:00
2016-11-04 17:20:44 +00:00
# source defaults
source $ad_hdl_dir / projects/ common/ altera/ sys_gen.tcl
2014-08-11 20:46:19 +00:00
