2020-03-17 08:15:01 +00:00
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# create board design
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# interface ports
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create_bd_port -dir I -type rst sys_rst
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4
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create_bd_port -dir I phy_sd
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create_bd_port -dir O -type rst phy_rst_n
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create_bd_port -dir I phy_dummy_port_in
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sgmii_rtl:1.0 sgmii
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sgmii_phyclk
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
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create_bd_port -dir I uart_sin
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create_bd_port -dir O uart_sout
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create_bd_port -dir O -from 7 -to 0 spi_csn_o
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create_bd_port -dir I -from 7 -to 0 spi_csn_i
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create_bd_port -dir I spi_clk_i
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create_bd_port -dir O spi_clk_o
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create_bd_port -dir I spi_sdo_i
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create_bd_port -dir O spi_sdo_o
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create_bd_port -dir I spi_sdi_i
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create_bd_port -dir I -from 31 -to 0 gpio0_i
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create_bd_port -dir O -from 31 -to 0 gpio0_o
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create_bd_port -dir O -from 31 -to 0 gpio0_t
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create_bd_port -dir I -from 31 -to 0 gpio1_i
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create_bd_port -dir O -from 31 -to 0 gpio1_o
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create_bd_port -dir O -from 31 -to 0 gpio1_t
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# io settings
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set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst]
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set_property -dict [list CONFIG.FREQ_HZ {100000000}] [get_bd_intf_ports sys_clk]
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set_property -dict [list CONFIG.FREQ_HZ {625000000}] [get_bd_intf_ports sgmii_phyclk]
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# instance: microblaze - processor
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ad_ip_instance microblaze sys_mb
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ad_ip_parameter sys_mb CONFIG.G_TEMPLATE_LIST 4
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ad_ip_parameter sys_mb CONFIG.C_DCACHE_FORCE_TAG_LUTRAM 1
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2022-05-02 11:35:31 +00:00
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ad_ip_parameter sys_mb CONFIG.C_ADDR_TAG_BITS 15
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ad_ip_parameter sys_mb CONFIG.C_CACHE_BYTE_SIZE 65536
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ad_ip_parameter sys_mb CONFIG.C_DCACHE_ADDR_TAG 15
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ad_ip_parameter sys_mb CONFIG.C_DCACHE_BYTE_SIZE 65536
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ad_ip_parameter sys_mb CONFIG.C_USE_BRANCH_TARGET_CACHE 1
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2020-03-17 08:15:01 +00:00
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# instance: microblaze - local memory & bus
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ad_ip_instance lmb_v10 sys_dlmb
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ad_ip_instance lmb_v10 sys_ilmb
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ad_ip_instance lmb_bram_if_cntlr sys_dlmb_cntlr
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ad_ip_parameter sys_dlmb_cntlr CONFIG.C_ECC {0}
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ad_ip_instance lmb_bram_if_cntlr sys_ilmb_cntlr
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ad_ip_parameter sys_ilmb_cntlr CONFIG.C_ECC {0}
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ad_ip_instance blk_mem_gen sys_lmb_bram
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ad_ip_parameter sys_lmb_bram CONFIG.Memory_Type True_Dual_Port_RAM
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ad_ip_parameter sys_lmb_bram CONFIG.use_bram_block BRAM_Controller
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# instance: microblaze- mdm
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ad_ip_instance mdm sys_mb_debug
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ad_ip_parameter sys_mb_debug CONFIG.C_USE_UART 1
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# instance: system reset/clocks
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ad_ip_instance proc_sys_reset sys_rstgen
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ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
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2022-05-02 11:35:31 +00:00
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ad_ip_instance proc_sys_reset sys_mb_rstgen
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ad_ip_parameter sys_mb_rstgen CONFIG.C_EXT_RST_WIDTH 1
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2020-03-17 08:15:01 +00:00
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ad_ip_instance proc_sys_reset sys_250m_rstgen
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ad_ip_parameter sys_250m_rstgen CONFIG.C_EXT_RST_WIDTH 1
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ad_ip_instance proc_sys_reset sys_500m_rstgen
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ad_ip_parameter sys_500m_rstgen CONFIG.C_EXT_RST_WIDTH 1
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2022-03-02 15:56:41 +00:00
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ad_ip_instance proc_sys_reset sys_hbm_rstgen
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ad_ip_parameter sys_hbm_rstgen CONFIG.C_EXT_RST_WIDTH 1
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# Clock for HBM
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ad_ip_instance clk_wiz hbm_clk_wiz [ list \
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PRIMITIVE {Auto} \
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PRIM_IN_FREQ {100} \
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CLKOUT1_REQUESTED_OUT_FREQ {450} \
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]
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2020-03-17 08:15:01 +00:00
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# instance: ddr4
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#
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ad_ip_instance ip:ddr4 axi_ddr_cntrl
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ad_ip_parameter axi_ddr_cntrl CONFIG.C0_CLOCK_BOARD_INTERFACE {default_100mhz_clk}
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ad_ip_parameter axi_ddr_cntrl CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram}
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ad_ip_parameter axi_ddr_cntrl ONFIG.RESET_BOARD_INTERFACE {reset}
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ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_Clamshell {true}
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ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_InputClockPeriod {10000}
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ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3}
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ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E}
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ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_DataWidth {72}
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ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI}
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ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_Ecc {true}
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ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_AxiDataWidth {512}
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ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_AxiAddressWidth {32}
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2022-05-02 11:35:31 +00:00
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ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ 200
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2020-03-17 08:15:01 +00:00
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ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ 250
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ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ 500
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ad_ip_parameter axi_ddr_cntrl CONFIG.C0.BANK_GROUP_WIDTH {1}
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ad_ip_parameter axi_ddr_cntrl CONFIG.C0.CS_WIDTH {2}
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ad_ip_instance proc_sys_reset axi_ddr_cntrl_rstgen
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# instance: default peripherals
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ad_ip_instance axi_ethernet axi_ethernet_0
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ad_ip_parameter axi_ethernet_0 CONFIG.DIFFCLK_BOARD_INTERFACE sgmii_phyclk
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ad_ip_parameter axi_ethernet_0 CONFIG.ETHERNET_BOARD_INTERFACE sgmii_lvds
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ad_ip_parameter axi_ethernet_0 CONFIG.MDIO_BOARD_INTERFACE mdio_mdc
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ad_ip_parameter axi_ethernet_0 CONFIG.PHYRST_BOARD_INTERFACE_DUMMY_PORT dummy_port_in
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ad_ip_parameter axi_ethernet_0 CONFIG.TXCSUM Full
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ad_ip_parameter axi_ethernet_0 CONFIG.RXCSUM Full
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ad_ip_parameter axi_ethernet_0 CONFIG.TXMEM 8k
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ad_ip_parameter axi_ethernet_0 CONFIG.RXMEM 8k
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ad_ip_instance axi_dma axi_ethernet_dma
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ad_ip_parameter axi_ethernet_dma CONFIG.c_include_mm2s_dre 1
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ad_ip_parameter axi_ethernet_dma CONFIG.c_sg_use_stsapp_length 1
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ad_ip_parameter axi_ethernet_dma CONFIG.c_include_s2mm_dre 1
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ad_ip_instance axi_iic axi_iic_main
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ad_ip_instance axi_uartlite axi_uart
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ad_ip_parameter axi_uart CONFIG.C_BAUDRATE 115200
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ad_ip_instance axi_timer axi_timer
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ad_ip_instance axi_quad_spi axi_spi
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ad_ip_parameter axi_spi CONFIG.C_USE_STARTUP 0
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ad_ip_parameter axi_spi CONFIG.C_NUM_SS_BITS 8
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ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 8
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ad_ip_instance axi_gpio axi_gpio
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ad_ip_parameter axi_gpio CONFIG.C_IS_DUAL 1
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ad_ip_parameter axi_gpio CONFIG.C_GPIO_WIDTH 32
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ad_ip_parameter axi_gpio CONFIG.C_GPIO2_WIDTH 32
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ad_ip_parameter axi_gpio CONFIG.C_INTERRUPT_PRESENT 1
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2022-05-02 11:35:31 +00:00
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ad_ip_instance util_ds_buf sys_cpu_clk_BUFGCE
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ad_ip_parameter sys_cpu_clk_BUFGCE CONFIG.C_BUF_TYPE {BUFGCE_DIV}
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ad_ip_parameter sys_cpu_clk_BUFGCE CONFIG.C_BUFGCE_DIV 2
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ad_connect sys_cpu_clk_BUFGCE/BUFGCE_CE VCC
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ad_connect sys_cpu_clk_BUFGCE/BUFGCE_CLR GND
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ad_connect sys_cpu_clk_BUFGCE/BUFGCE_I sys_mb_clk
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ad_connect sys_cpu_clk sys_cpu_clk_BUFGCE/BUFGCE_O
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2020-03-17 08:15:01 +00:00
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# instance: interrupt
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ad_ip_instance axi_intc axi_intc
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ad_ip_parameter axi_intc CONFIG.C_HAS_FAST 0
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ad_ip_instance xlconcat sys_concat_intc
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ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16
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# ddr4
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ad_connect sys_rst axi_ddr_cntrl/sys_rst
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ad_connect sys_clk axi_ddr_cntrl/C0_SYS_CLK
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ad_connect ddr4 axi_ddr_cntrl/C0_DDR4
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ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ddr_cntrl_rstgen/ext_reset_in
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ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_rstgen/ext_reset_in
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ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_250m_rstgen/ext_reset_in
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ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_500m_rstgen/ext_reset_in
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2022-03-02 15:56:41 +00:00
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ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_hbm_rstgen/ext_reset_in
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2020-03-17 08:15:01 +00:00
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ad_connect sys_mem_clk axi_ddr_cntrl/c0_ddr4_ui_clk
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ad_connect sys_mem_clk axi_ddr_cntrl_rstgen/slowest_sync_clk
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2022-05-02 11:35:31 +00:00
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ad_connect sys_mb_clk axi_ddr_cntrl/addn_ui_clkout1
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ad_connect sys_mb_clk sys_mb_rstgen/slowest_sync_clk
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2020-03-17 08:15:01 +00:00
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ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
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ad_connect sys_mem_resetn axi_ddr_cntrl_rstgen/peripheral_aresetn
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ad_connect sys_mem_resetn axi_ddr_cntrl/c0_ddr4_aresetn
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ad_connect sys_250m_clk axi_ddr_cntrl/addn_ui_clkout2
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ad_connect sys_250m_clk sys_250m_rstgen/slowest_sync_clk
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ad_connect sys_500m_clk axi_ddr_cntrl/addn_ui_clkout3
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ad_connect sys_500m_clk sys_500m_rstgen/slowest_sync_clk
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2022-03-02 15:56:41 +00:00
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ad_connect sys_hbm_clk hbm_clk_wiz/clk_out1
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ad_connect sys_hbm_clk sys_hbm_rstgen/slowest_sync_clk
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2020-03-17 08:15:01 +00:00
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ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
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ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
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ad_connect sys_250m_reset sys_250m_rstgen/peripheral_reset
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ad_connect sys_250m_resetn sys_250m_rstgen/peripheral_aresetn
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ad_connect sys_500m_reset sys_500m_rstgen/peripheral_reset
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ad_connect sys_500m_resetn sys_500m_rstgen/peripheral_aresetn
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# generic system clocks pointers
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2022-05-02 11:35:31 +00:00
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set sys_cpu_clk [get_bd_pins sys_cpu_clk_BUFGCE/BUFGCE_O]
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set sys_mb_clk [get_bd_nets axi_ddr_cntrl/addn_ui_clkout1]
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2020-03-17 08:15:01 +00:00
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set sys_dma_clk [get_bd_nets sys_250m_clk]
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set sys_iodelay_clk [get_bd_nets sys_500m_clk]
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2022-03-02 15:56:41 +00:00
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set sys_hbm_clk [get_bd_pins hbm_clk_wiz/clk_out1]
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2020-03-17 08:15:01 +00:00
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set sys_cpu_reset [get_bd_nets sys_cpu_reset]
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set sys_cpu_resetn [get_bd_pins sys_rstgen/peripheral_aresetn]
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set sys_dma_reset [get_bd_nets sys_250m_reset]
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set sys_dma_resetn [get_bd_nets sys_250m_resetn]
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set sys_iodelay_reset [get_bd_nets sys_500m_reset]
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set sys_iodelay_resetn [get_bd_nets sys_500m_resetn]
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2022-03-02 15:56:41 +00:00
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set sys_hbm_reset [get_bd_pins sys_hbm_rstgen/peripheral_reset]
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set sys_hbm_resetn [get_bd_pins sys_hbm_rstgen/peripheral_aresetn]
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# clock gen connections
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ad_connect $sys_cpu_clk hbm_clk_wiz/clk_in1
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2020-03-17 08:15:01 +00:00
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# microblaze debug & interrupt
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2022-05-02 11:35:31 +00:00
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ad_connect sys_mb_clk sys_mb/Clk
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ad_connect sys_mb_clk sys_dlmb/LMB_Clk
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ad_connect sys_mb_clk sys_ilmb/LMB_Clk
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ad_connect sys_mb_clk sys_dlmb_cntlr/LMB_Clk
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ad_connect sys_mb_clk sys_ilmb_cntlr/LMB_Clk
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ad_connect sys_mb_rstgen/mb_reset sys_mb/Reset
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ad_connect sys_mb_rstgen/bus_struct_reset sys_dlmb/SYS_Rst
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ad_connect sys_mb_rstgen/bus_struct_reset sys_ilmb/SYS_Rst
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ad_connect sys_mb_rstgen/bus_struct_reset sys_dlmb_cntlr/LMB_Rst
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ad_connect sys_mb_rstgen/bus_struct_reset sys_ilmb_cntlr/LMB_Rst
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2020-03-17 08:15:01 +00:00
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ad_connect sys_mb/DLMB sys_dlmb/LMB_M
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ad_connect sys_mb/ILMB sys_ilmb/LMB_M
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ad_connect sys_dlmb/LMB_Sl_0 sys_dlmb_cntlr/SLMB
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ad_connect sys_ilmb/LMB_Sl_0 sys_ilmb_cntlr/SLMB
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ad_connect sys_dlmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTA
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ad_connect sys_ilmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTB
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ad_connect sys_mb_debug/Debug_SYS_Rst sys_rstgen/mb_debug_sys_rst
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ad_connect sys_mb_debug/MBDEBUG_0 sys_mb/DEBUG
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ad_connect axi_intc/interrupt sys_mb/INTERRUPT
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ad_connect axi_intc/intr sys_concat_intc/dout
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# ethernet
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ad_connect sgmii axi_ethernet_0/sgmii
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ad_connect sgmii_phyclk axi_ethernet_0/lvds_clk
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ad_connect mdio axi_ethernet_0/mdio
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ad_connect phy_sd axi_ethernet_0/signal_detect
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ad_connect phy_dummy_port_in axi_ethernet_0/dummy_port_in
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ad_connect sys_cpu_clk axi_ethernet_0/axis_clk
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ad_connect axi_ethernet_0/s_axis_txd axi_ethernet_dma/M_AXIS_MM2S
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ad_connect axi_ethernet_0/s_axis_txc axi_ethernet_dma/M_AXIS_CNTRL
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ad_connect axi_ethernet_0/m_axis_rxd axi_ethernet_dma/S_AXIS_S2MM
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ad_connect axi_ethernet_0/m_axis_rxs axi_ethernet_dma/S_AXIS_STS
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ad_connect axi_ethernet_0/axi_txd_arstn axi_ethernet_dma/mm2s_prmry_reset_out_n
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ad_connect axi_ethernet_0/axi_txc_arstn axi_ethernet_dma/mm2s_cntrl_reset_out_n
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ad_connect axi_ethernet_0/axi_rxd_arstn axi_ethernet_dma/s2mm_prmry_reset_out_n
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ad_connect axi_ethernet_0/axi_rxs_arstn axi_ethernet_dma/s2mm_sts_reset_out_n
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# system id
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ad_ip_instance axi_sysid axi_sysid_0
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ad_ip_instance sysid_rom rom_sys_0
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ad_connect axi_sysid_0/rom_addr rom_sys_0/rom_addr
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ad_connect axi_sysid_0/sys_rom_data rom_sys_0/rom_data
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ad_connect sys_cpu_clk rom_sys_0/clk
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# iic, spi and gpio
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ad_connect iic_main axi_iic_main/iic
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ad_connect uart_sin axi_uart/rx
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ad_connect uart_sout axi_uart/tx
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ad_connect spi_csn_i axi_spi/ss_i
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ad_connect spi_csn_o axi_spi/ss_o
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ad_connect spi_clk_i axi_spi/sck_i
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ad_connect spi_clk_o axi_spi/sck_o
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ad_connect spi_sdo_i axi_spi/io0_i
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ad_connect spi_sdo_o axi_spi/io0_o
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ad_connect spi_sdi_i axi_spi/io1_i
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ad_connect gpio0_i axi_gpio/gpio_io_i
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ad_connect gpio0_o axi_gpio/gpio_io_o
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ad_connect gpio0_t axi_gpio/gpio_io_t
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ad_connect gpio1_i axi_gpio/gpio2_io_i
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ad_connect gpio1_o axi_gpio/gpio2_io_o
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ad_connect gpio1_t axi_gpio/gpio2_io_t
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ad_connect sys_cpu_clk axi_spi/ext_spi_clk
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# defaults (interrupts)
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ad_connect sys_concat_intc/In0 axi_timer/interrupt
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ad_connect sys_concat_intc/In1 axi_ethernet_0/interrupt
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ad_connect sys_concat_intc/In2 axi_ethernet_dma/mm2s_introut
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ad_connect sys_concat_intc/In3 axi_ethernet_dma/s2mm_introut
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ad_connect sys_concat_intc/In4 axi_uart/interrupt
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ad_connect sys_concat_intc/In5 GND
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ad_connect sys_concat_intc/In6 GND
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ad_connect sys_concat_intc/In7 GND
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ad_connect sys_concat_intc/In8 GND
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ad_connect sys_concat_intc/In9 axi_iic_main/iic2intc_irpt
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ad_connect sys_concat_intc/In10 axi_spi/ip2intc_irpt
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ad_connect sys_concat_intc/In11 axi_gpio/ip2intc_irpt
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ad_connect sys_concat_intc/In12 GND
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ad_connect sys_concat_intc/In13 GND
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ad_connect sys_concat_intc/In14 GND
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ad_connect sys_concat_intc/In15 GND
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# interconnect - processor
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ad_cpu_interconnect 0x40C00000 axi_ethernet_0
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ad_cpu_interconnect 0x41E10000 axi_ethernet_dma
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ad_cpu_interconnect 0x40000000 axi_gpio
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ad_cpu_interconnect 0x40600000 axi_uart
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ad_cpu_interconnect 0x41200000 axi_intc
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ad_cpu_interconnect 0x41C00000 axi_timer
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ad_cpu_interconnect 0x41600000 axi_iic_main
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ad_cpu_interconnect 0x45000000 axi_sysid_0
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ad_cpu_interconnect 0x44A70000 axi_spi
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ad_cpu_interconnect 0x41400000 sys_mb_debug
|
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ad_cpu_interconnect 0x45100000 axi_ddr_cntrl C0_DDR4_S_AXI_CTRL
|
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|
|
### Workaround for DDR controller with control interface
|
|
|
|
|
### DDR contoller control interface runs at UI clock not CPU clock
|
2022-05-02 11:35:31 +00:00
|
|
|
set_property -dict [list CONFIG.NUM_CLKS {3}] [get_bd_cells axi_cpu_interconnect]
|
2020-03-17 08:15:01 +00:00
|
|
|
ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk axi_cpu_interconnect/aclk1
|
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|
|
|
2022-05-02 11:35:31 +00:00
|
|
|
### Peripheral Data Interface runs at the sys_mb_clk frequency
|
|
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|
|
ad_connect sys_mb_clk axi_cpu_interconnect/aclk2
|
|
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|
|
|
2020-03-17 08:15:01 +00:00
|
|
|
# interconnect - memory
|
|
|
|
|
|
|
|
|
|
ad_mem_hp0_interconnect sys_mem_clk axi_ddr_cntrl/C0_DDR4_S_AXI
|
2022-05-02 11:35:31 +00:00
|
|
|
ad_mem_hp0_interconnect sys_mb_clk sys_mb/M_AXI_DC
|
|
|
|
|
ad_mem_hp0_interconnect sys_mb_clk sys_mb/M_AXI_IC
|
2020-03-17 08:15:01 +00:00
|
|
|
ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_SG
|
|
|
|
|
ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_MM2S
|
|
|
|
|
ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_S2MM
|
|
|
|
|
|
|
|
|
|
create_bd_addr_seg -range 0x80000 -offset 0x0 [get_bd_addr_spaces sys_mb/Data] \
|
|
|
|
|
[get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_dlmb_cntlr
|
|
|
|
|
create_bd_addr_seg -range 0x80000 -offset 0x0 [get_bd_addr_spaces sys_mb/Instruction] \
|
|
|
|
|
[get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_ilmb_cntlr
|
|
|
|
|
|
