2018-04-13 16:09:57 +00:00
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2019-05-31 07:27:14 +00:00
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# instantiate the base design
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2018-04-13 16:09:57 +00:00
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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2019-05-31 07:27:14 +00:00
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# load all the FIFO related proccesses
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2018-04-13 16:09:57 +00:00
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source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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2019-05-31 07:27:14 +00:00
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# NOTE: to swap the resources comment the two lines above, and uncomment to two line below
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#source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl
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#source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
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2019-05-30 13:45:10 +00:00
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# the DAC FIFO has a 500KSMP depth - 1 Mbyte
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set dac_fifo_address_width 15
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# by default PLDDR is used (1 Gbyte), this varible should be ignored
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2019-05-31 07:27:14 +00:00
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set adc_fifo_address_width 15
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2019-05-30 13:45:10 +00:00
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2018-04-13 16:09:57 +00:00
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source ../common/fmcomms11_bd.tcl
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2019-06-28 08:41:21 +00:00
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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set sys_cstring "sys rom custom string placeholder"
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sysid_gen_sys_init_file $sys_cstring
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