pluto_hdl_adi/library/util_clkdiv/util_clkdiv.v

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// ***************************************************************************
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// Divides the input clock to 4 if clk_sel is 0 or 2 if clk_sel is 1
// IP uses BUFR and BUFGMUX primitives
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module util_clkdiv (
  input   clk,
  input   clk_sel,
  output  clk_out
 );

  wire clk_div_2_s;
  wire clk_div_4_s;

  BUFR #(
    .BUFR_DIVIDE("2"),
    .SIM_DEVICE("7SERIES")
  ) clk_divide_2 (
    .I(clk),
    .CE(1),
    .CLR(0),
    .O(clk_div_2_s));

  BUFR #(
    .BUFR_DIVIDE("4"),
    .SIM_DEVICE("7SERIES")
  ) clk_divide_4 (
    .I(clk),
    .CE(1),
    .CLR(0),
    .O(clk_div_4_s));

  BUFGMUX i_div_clk_gbuf (
    .I0(clk_div_4_s), // 1-bit input: Clock input (S=0)
    .I1(clk_div_2_s), // 1-bit input: Clock input (S=1)
    .S(clk_sel),
    .O (clk_out));

endmodule  // util_clkdiv