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pluto_hdl_adi/projects/common/zc706/zc706_system_plddr3.tcl

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Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# pl ddr3 (use only when dma is not capable of keeping up).
# generic fifo interface - existence is oblivious to software.
proc p_plddr3_fifo {p_name m_name adc_data_width} {
global ad_hdl_dir
set p_instance [get_bd_cells $p_name]
set c_instance [current_bd_instance .]
current_bd_instance $p_instance
set m_instance [create_bd_cell -type hier $m_name]
current_bd_instance $m_instance
create_bd_pin -dir I -type rst sys_rst
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
create_bd_pin -dir I adc_rst
create_bd_pin -dir I -type clk adc_clk
create_bd_pin -dir I adc_wr
create_bd_pin -dir I -from [expr ($adc_data_width-1)] -to 0 adc_wdata
create_bd_pin -dir O adc_wovf
create_bd_pin -dir I -type clk dma_clk
create_bd_pin -dir O dma_wr
create_bd_pin -dir O -from 63 -to 0 dma_wdata
create_bd_pin -dir I dma_wready
create_bd_pin -dir I dma_xfer_req
create_bd_pin -dir O -from 3 -to 0 dma_xfer_status
zc706: Updated common design to 2015.4
2016-03-15 13:16:36 +00:00
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl
set axi_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_rstgen]
set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_rstgen
set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_rstgen
set axi_adcfifo [create_bd_cell -type ip -vlnv analog.com:user:axi_adcfifo:1.0 axi_adcfifo]
set_property -dict [list CONFIG.ADC_DATA_WIDTH $adc_data_width] $axi_adcfifo
set_property -dict [list CONFIG.DMA_DATA_WIDTH {64}] $axi_adcfifo
set_property -dict [list CONFIG.AXI_DATA_WIDTH {512}] $axi_adcfifo
set_property -dict [list CONFIG.DMA_READY_ENABLE {1}] $axi_adcfifo
set_property -dict [list CONFIG.AXI_SIZE {6}] $axi_adcfifo
set_property -dict [list CONFIG.AXI_LENGTH {4}] $axi_adcfifo
set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_adcfifo
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_adcfifo
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
set_property -dict [list CONFIG.AXI_BYTE_WIDTH {64}] $axi_adcfifo
ad_connect sys_rst axi_ddr_cntrl/sys_rst
ad_connect sys_clk axi_ddr_cntrl/SYS_CLK
ad_connect ddr3 axi_ddr_cntrl/DDR3
ad_connect axi_ddr_cntrl/S_AXI axi_adcfifo/axi
ad_connect adc_rst axi_adcfifo/adc_rst
ad_connect adc_rst axi_rstgen/ext_reset_in
zc706_system_plddr3.tcl : Add integration process for the AXI_DAC_FIFO
2016-04-19 08:30:52 +00:00
ad_connect adc_clk axi_adcfifo/adc_clk
ad_connect adc_wr axi_adcfifo/adc_wr
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_connect adc_wdata axi_adcfifo/adc_wdata
ad_connect adc_wovf axi_adcfifo/adc_wovf
ad_connect dma_clk axi_adcfifo/dma_clk
ad_connect dma_wr axi_adcfifo/dma_wr
ad_connect dma_wdata axi_adcfifo/dma_wdata
ad_connect dma_wready axi_adcfifo/dma_wready
ad_connect dma_xfer_req axi_adcfifo/dma_xfer_req
ad_connect dma_xfer_status axi_adcfifo/dma_xfer_status
ad_connect axi_clk axi_ddr_cntrl/ui_clk
ad_connect axi_clk axi_adcfifo/axi_clk
ad_connect axi_clk axi_rstgen/slowest_sync_clk
ad_connect axi_resetn axi_rstgen/peripheral_aresetn
ad_connect axi_resetn axi_adcfifo/axi_resetn
ad_connect axi_resetn axi_ddr_cntrl/aresetn
ad_connect axi_ddr_cntrl/device_temp_i GND
current_bd_instance $c_instance
}
zc706_system_plddr3.tcl : Add integration process for the AXI_DAC_FIFO
2016-04-19 08:30:52 +00:00
proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
global ad_hdl_dir
set p_instance [get_bd_cells $p_name]
set c_instance [current_bd_instance .]
current_bd_instance $p_instance
set m_instance [create_bd_cell -type hier $m_name]
current_bd_instance $m_instance
create_bd_pin -dir I -type rst sys_rst
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
create_bd_pin -dir I dac_rst
create_bd_pin -dir I -type clk dac_clk
create_bd_pin -dir I dac_valid
create_bd_pin -dir O -from [expr ($dac_data_width-1)] -to 0 dac_data
create_bd_pin -dir O dac_dunf
create_bd_pin -dir O dac_dovf
create_bd_pin -dir O dac_xfer_out
create_bd_pin -dir I -type clk dma_clk
create_bd_pin -dir I dma_rvalid
create_bd_pin -dir I -from [expr ($dma_data_width-1)] -to 0 dma_rdata
create_bd_pin -dir O dma_rready
create_bd_pin -dir I dma_xfer_req
create_bd_pin -dir I dma_xfer_last
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl]
set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl
set axi_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_rstgen]
set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_rstgen
set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_rstgen
set axi_dacfifo [create_bd_cell -type ip -vlnv analog.com:user:axi_dacfifo:1.0 axi_dacfifo]
set_property -dict [list CONFIG.DAC_DATA_WIDTH $dac_data_width] $axi_dacfifo
set_property -dict [list CONFIG.DMA_DATA_WIDTH $dma_data_width] $axi_dacfifo
set_property -dict [list CONFIG.AXI_DATA_WIDTH {512}] $axi_dacfifo
set_property -dict [list CONFIG.AXI_WR_SIZE {6}] $axi_dacfifo
set_property -dict [list CONFIG.AXI_WR_LENGTH {3}] $axi_dacfifo
set_property -dict [list CONFIG.AXI_RD_SIZE {6}] $axi_dacfifo
set_property -dict [list CONFIG.AXI_RD_LENGTH {15}] $axi_dacfifo
set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_dacfifo
set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_dacfifo
## clock and reset
ad_connect sys_clk axi_ddr_cntrl/SYS_CLK
ad_connect sys_rst axi_ddr_cntrl/sys_rst
ad_connect axi_clk axi_ddr_cntrl/ui_clk
ad_connect axi_clk axi_dacfifo/axi_clk
ad_connect axi_clk axi_rstgen/slowest_sync_clk
ad_connect dac_clk axi_dacfifo/dac_clk
ad_connect dma_clk axi_dacfifo/dma_clk
ad_connect axi_resetn axi_rstgen/peripheral_aresetn
ad_connect axi_resetn axi_dacfifo/axi_resetn
ad_connect axi_resetn axi_ddr_cntrl/aresetn
ad_connect dac_rst axi_dacfifo/dac_reset
ad_connect dac_rst axi_rstgen/ext_reset_in
## interfaces
ad_connect ddr3 axi_ddr_cntrl/DDR3
ad_connect axi_ddr_cntrl/S_AXI axi_dacfifo/axi
ad_connect dma_rvalid axi_dacfifo/dma_valid
ad_connect dma_rready axi_dacfifo/dma_ready
ad_connect dma_rdata axi_dacfifo/dma_data
ad_connect dma_xfer_req axi_dacfifo/dma_xfer_req
ad_connect dma_xfer_last axi_dacfifo/dma_xfer_last
ad_connect dac_valid axi_dacfifo/dac_valid
ad_connect dac_data axi_dacfifo/dac_data
ad_connect dac_dunf axi_dacfifo/dac_dunf
ad_connect dac_dovf axi_dacfifo/dac_dovf
ad_connect dac_xfer_out axi_dacfifo/dac_xfer_out
ad_connect axi_ddr_cntrl/device_temp_i GND
current_bd_instance $c_instance
}