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pluto_hdl_adi/projects/fmcomms2/c5soc/system_bd.qsys

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c5soc: initial a5soc copy
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<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
}
fmcomms2/c5soc: initial checkin
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element axi_ad9361
c5soc: initial a5soc copy
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{
datum _sortIndex
{
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value = "5";
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type = "int";
}
}
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element axi_dmac_adc
c5soc: initial a5soc copy
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{
datum _sortIndex
{
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value = "7";
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type = "int";
}
}
fmcomms2/c5soc: initial checkin
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element axi_dmac_dac
c5soc: initial a5soc copy
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{
datum _sortIndex
{
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value = "6";
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type = "int";
}
}
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element sys_id.control_slave
c5soc: initial a5soc copy
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{
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datum _lockedAddress
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{
value = "1";
type = "boolean";
}
datum baseAddress
{
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value = "65536";
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type = "String";
}
}
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element sys_gpio.external_connection
c5soc: initial a5soc copy
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{
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datum _tags
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{
fmcomms2/c5soc: initial checkin
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value = "";
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type = "String";
}
}
element sys_hps.f2h_axi_slave
{
datum baseAddress
{
value = "0";
type = "String";
}
}
element sys_hps.f2h_sdram0_data
{
datum baseAddress
{
value = "0";
type = "String";
}
}
element sys_int_mem.s1
{
datum baseAddress
{
value = "0";
type = "String";
}
}
element sys_gpio.s1
{
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datum _lockedAddress
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{
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value = "1";
type = "boolean";
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}
datum baseAddress
{
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value = "65664";
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type = "String";
}
}
fmcomms2/c5soc: initial checkin
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element axi_dmac_dac.s_axi
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{
datum baseAddress
{
value = "16384";
type = "String";
}
}
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element axi_ad9361.s_axi
c5soc: initial a5soc copy
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{
datum baseAddress
{
AD9361: Altera, modified address width so that all registers are accessible Modified qsys project with the new address span
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value = "131072";
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type = "String";
}
}
fmcomms2/c5soc: initial checkin
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element axi_dmac_adc.s_axi
c5soc: initial a5soc copy
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{
datum baseAddress
{
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value = "0";
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type = "String";
}
}
element sys_clk
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element sys_gpio
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
element sys_hps
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element sys_id
{
datum _sortIndex
{
value = "3";
type = "int";
}
}
element sys_int_mem
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="FIFO" />
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<parameter name="device" value="5CSXFC6D6F31C8ES" />
<parameter name="deviceFamily" value="Cyclone V" />
<parameter name="deviceSpeedGrade" value="8_H6" />
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<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
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<parameter name="maxAdditionalLatency" value="2" />
<parameter name="projectName" value="fmcomms2_c5soc.qpf" />
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<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="sys_clk.clk_in" type="clock" dir="end" />
<interface name="reset" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
<interface
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name="sys_hps_memory"
internal="sys_hps.memory"
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type="conduit"
dir="end" />
<interface
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name="sys_hps_hps_io"
internal="sys_hps.hps_io"
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type="conduit"
dir="end" />
<interface
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name="sys_gpio_external_connection"
internal="sys_gpio.external_connection"
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type="conduit"
dir="end" />
<interface
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name="sys_hps_h2f_reset"
internal="sys_hps.h2f_reset"
type="reset"
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dir="start" />
fmcomms2/c5soc: initial checkin
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<interface name="hps_0_f2h_cold_reset_req" internal="sys_hps.f2h_cold_reset_req" />
c5soc: initial a5soc copy
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<interface
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name="hps_0_f2h_debug_reset_req"
internal="sys_hps.f2h_debug_reset_req" />
<interface name="hps_0_f2h_warm_reset_req" internal="sys_hps.f2h_warm_reset_req" />
<interface name="sys_hps_f2h_stm_hw_events" internal="sys_hps.f2h_stm_hw_events" />
<interface name="axi_ad9361_0_rx_clock" internal="axi_ad9361.rx_clock" />
<interface name="axi_ad9361_0_rx_if" internal="axi_ad9361.rx_if" />
<interface name="axi_ad9361_0_tx_clock" internal="axi_ad9361.tx_clock" />
<interface name="axi_ad9361_0_tx_if" internal="axi_ad9361.tx_if" />
<interface name="axi_ad9361_0_adc_dma_if" internal="axi_ad9361.adc_dma_if" />
<interface name="axi_ad9361_0_dac_dma_if" internal="axi_ad9361.dac_dma_if" />
<interface name="axi_ad9361_0_adc_mon_if" internal="axi_ad9361.adc_mon_if" />
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<interface
name="sys_hps_spim0"
internal="sys_hps.spim0"
type="conduit"
dir="end" />
<interface
name="sys_hps_spim0_sclk_out"
internal="sys_hps.spim0_sclk_out"
type="clock"
dir="start" />
<interface
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name="axi_ad9361_device_clock"
internal="axi_ad9361.device_clock"
type="clock"
dir="end" />
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<interface
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name="axi_ad9361_device_if"
internal="axi_ad9361.device_if"
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type="conduit"
dir="end" />
<interface
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name="axi_ad9361_master_if"
internal="axi_ad9361.master_if"
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type="conduit"
dir="end" />
<interface
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name="axi_ad9361_dma_if"
internal="axi_ad9361.dma_if"
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type="conduit"
dir="end" />
<interface
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name="axi_ad9361_debug_if"
internal="axi_ad9361.debug_if"
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type="conduit"
dir="end" />
<interface
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name="axi_dmac_dac_fifo_rd_clock"
internal="axi_dmac_dac.fifo_rd_clock"
type="clock"
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dir="end" />
<interface
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name="axi_dmac_dac_fifo_rd_if"
internal="axi_dmac_dac.fifo_rd_if"
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type="conduit"
dir="end" />
<interface
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name="axi_dmac_adc_fifo_wr_clock"
internal="axi_dmac_adc.fifo_wr_clock"
type="clock"
dir="end" />
<interface
name="axi_dmac_adc_fifo_wr_if"
internal="axi_dmac_adc.fifo_wr_if"
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type="conduit"
dir="end" />
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<module kind="clock_source" version="13.1" enabled="1" name="sys_clk">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
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<module kind="altera_hps" version="13.1" enabled="1" name="sys_hps">
<parameter name="MEM_VENDOR" value="JEDEC" />
<parameter name="MEM_FORMAT" value="DISCRETE" />
<parameter name="RDIMM_CONFIG" value="0000000000000000" />
<parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
<parameter name="DISCRETE_FLY_BY" value="true" />
<parameter name="DEVICE_DEPTH" value="1" />
<parameter name="MEM_MIRROR_ADDRESSING" value="0" />
<parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
<parameter name="MEM_ROW_ADDR_WIDTH" value="15" />
<parameter name="MEM_COL_ADDR_WIDTH" value="10" />
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<parameter name="MEM_DQ_WIDTH" value="32" />
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<parameter name="MEM_DQ_PER_DQS" value="8" />
<parameter name="MEM_BANKADDR_WIDTH" value="3" />
<parameter name="MEM_IF_DM_PINS_EN" value="true" />
<parameter name="MEM_IF_DQSN_EN" value="true" />
<parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
<parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
<parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
<parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
<parameter name="MEM_CK_WIDTH" value="1" />
<parameter name="MEM_CS_WIDTH" value="1" />
<parameter name="MEM_CLK_EN_WIDTH" value="1" />
<parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
<parameter name="NEXTGEN" value="true" />
<parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
<parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
<parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
<parameter name="MEM_VERBOSE" value="true" />
<parameter name="PINGPONGPHY_EN" value="false" />
<parameter name="REFRESH_BURST_VALIDATION" value="false" />
<parameter name="MEM_BL" value="OTF" />
<parameter name="MEM_BT" value="Sequential" />
<parameter name="MEM_ASR" value="Manual" />
<parameter name="MEM_SRT" value="Normal" />
<parameter name="MEM_PD" value="DLL off" />
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<parameter name="MEM_DRV_STR" value="RZQ/7" />
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<parameter name="MEM_DLL_EN" value="true" />
<parameter name="MEM_RTT_NOM" value="RZQ/4" />
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<parameter name="MEM_RTT_WR" value="RZQ/4" />
<parameter name="MEM_WTCL" value="8" />
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<parameter name="MEM_ATCL" value="Disabled" />
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<parameter name="MEM_TCL" value="11" />
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<parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
<parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
<parameter name="MEM_INIT_EN" value="false" />
<parameter name="MEM_INIT_FILE" value="" />
<parameter name="DAT_DATA_WIDTH" value="32" />
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<parameter name="TIMING_TIS" value="180" />
<parameter name="TIMING_TIH" value="140" />
<parameter name="TIMING_TDS" value="30" />
<parameter name="TIMING_TDH" value="65" />
<parameter name="TIMING_TDQSQ" value="125" />
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<parameter name="TIMING_TQHS" value="300" />
<parameter name="TIMING_TQH" value="0.38" />
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<parameter name="TIMING_TDQSCK" value="255" />
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<parameter name="TIMING_TDQSCKDS" value="450" />
<parameter name="TIMING_TDQSCKDM" value="900" />
<parameter name="TIMING_TDQSCKDL" value="1200" />
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<parameter name="TIMING_TDQSS" value="0.25" />
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<parameter name="TIMING_TDQSH" value="0.35" />
<parameter name="TIMING_TQSH" value="0.4" />
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<parameter name="TIMING_TDSH" value="0.2" />
<parameter name="TIMING_TDSS" value="0.2" />
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<parameter name="MEM_TINIT_US" value="500" />
<parameter name="MEM_TMRD_CK" value="4" />
<parameter name="MEM_TRAS_NS" value="35.0" />
<parameter name="MEM_TRCD_NS" value="13.75" />
<parameter name="MEM_TRP_NS" value="13.75" />
<parameter name="MEM_TREFI_US" value="7.8" />
<parameter name="MEM_TRFC_NS" value="260.0" />
<parameter name="CFG_TCCD_NS" value="2.5" />
<parameter name="MEM_TWR_NS" value="15.0" />
<parameter name="MEM_TWTR" value="4" />
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<parameter name="MEM_TFAW_NS" value="30.0" />
<parameter name="MEM_TRRD_NS" value="7.5" />
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<parameter name="MEM_TRTP_NS" value="7.5" />
<parameter name="POWER_OF_TWO_BUS" value="false" />
<parameter name="SOPC_COMPAT_RESET" value="false" />
<parameter name="AVL_MAX_SIZE" value="4" />
<parameter name="BYTE_ENABLE" value="true" />
<parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
<parameter name="CTL_DEEP_POWERDN_EN" value="false" />
<parameter name="CTL_SELF_REFRESH_EN" value="false" />
<parameter name="AUTO_POWERDN_EN" value="false" />
<parameter name="AUTO_PD_CYCLES" value="0" />
<parameter name="CTL_USR_REFRESH_EN" value="false" />
<parameter name="CTL_AUTOPCH_EN" value="false" />
<parameter name="CTL_ZQCAL_EN" value="false" />
<parameter name="ADDR_ORDER" value="0" />
<parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
<parameter name="CONTROLLER_LATENCY" value="5" />
<parameter name="CFG_REORDER_DATA" value="true" />
<parameter name="STARVE_LIMIT" value="10" />
<parameter name="CTL_CSR_ENABLED" value="false" />
<parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
<parameter name="CTL_ECC_ENABLED" value="false" />
<parameter name="CTL_HRB_ENABLED" value="false" />
<parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
<parameter name="MULTICAST_EN" value="false" />
<parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
<parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
<parameter name="DEBUG_MODE" value="false" />
<parameter name="ENABLE_BURST_MERGE" value="false" />
<parameter name="CTL_ENABLE_BURST_INTERRUPT" value="true" />
<parameter name="CTL_ENABLE_BURST_TERMINATE" value="true" />
<parameter name="LOCAL_ID_WIDTH" value="8" />
<parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
<parameter name="MAX_PENDING_WR_CMD" value="8" />
<parameter name="MAX_PENDING_RD_CMD" value="16" />
<parameter name="USE_MM_ADAPTOR" value="true" />
<parameter name="USE_AXI_ADAPTOR" value="false" />
<parameter name="HCX_COMPAT_MODE" value="false" />
<parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
<parameter name="CTL_CSR_READ_ONLY" value="1" />
<parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
<parameter name="NUM_OF_PORTS" value="1" />
<parameter name="ENABLE_BONDING" value="false" />
<parameter name="ENABLE_USER_ECC" value="false" />
<parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
<parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
<parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
<parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
<parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
<parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
<parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
<parameter name="REF_CLK_FREQ" value="25.0" />
<parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
<parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
<parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
<parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
<parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
<parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
<parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
<parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
<parameter name="PLL_CLK_PARAM_VALID" value="false" />
<parameter name="ENABLE_EXTRA_REPORTING" value="false" />
<parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
<parameter name="ENABLE_ISS_PROBES" value="false" />
<parameter name="CALIB_REG_WIDTH" value="8" />
<parameter name="USE_SEQUENCER_BFM" value="false" />
<parameter name="DEFAULT_FAST_SIM_MODEL" value="true" />
<parameter name="PLL_SHARING_MODE" value="None" />
<parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
<parameter name="EXPORT_AFI_HALF_CLK" value="false" />
<parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
<parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
<parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
<parameter name="USE_FAKE_PHY" value="false" />
<parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
<parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
<parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
<parameter name="TRACKING_ERROR_TEST" value="false" />
<parameter name="TRACKING_WATCH_TEST" value="false" />
<parameter name="MARGIN_VARIATION_TEST" value="false" />
<parameter name="EXTRA_SETTINGS" value="" />
<parameter name="MEM_DEVICE" value="MISSING_MODEL" />
<parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
<parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
<parameter name="SEQUENCER_TYPE" value="NIOS" />
<parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
<parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
<parameter name="PHY_ONLY" value="false" />
<parameter name="SEQ_MODE" value="0" />
<parameter name="ADVANCED_CK_PHASES" value="false" />
<parameter name="COMMAND_PHASE" value="0.0" />
<parameter name="MEM_CK_PHASE" value="0.0" />
<parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
<parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
<parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
<parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
<parameter name="PLL_LOCATION" value="Top_Bottom" />
<parameter name="SKIP_MEM_INIT" value="true" />
<parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
<parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
<parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
<parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
<parameter name="CALIBRATION_MODE" value="Skip" />
<parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
<parameter name="READ_FIFO_SIZE" value="8" />
<parameter name="PHY_CSR_ENABLED" value="false" />
<parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
<parameter name="USER_DEBUG_LEVEL" value="1" />
<parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
<parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
<parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
<parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
<parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
<parameter name="TIMING_BOARD_TIS" value="0.0" />
<parameter name="TIMING_BOARD_TIH" value="0.0" />
<parameter name="TIMING_BOARD_TDS" value="0.0" />
<parameter name="TIMING_BOARD_TDH" value="0.0" />
<parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
<parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
<parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
<parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
<parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
<parameter name="PACKAGE_DESKEW" value="false" />
<parameter name="AC_PACKAGE_DESKEW" value="false" />
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<parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.03" />
<parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.02" />
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.09" />
<parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.16" />
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<parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
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<parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01" />
<parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.08" />
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<parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
fmcomms2/c5soc: initial checkin
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<parameter name="TIMING_BOARD_AC_SKEW" value="0.03" />
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<parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
<parameter name="RATE" value="Full" />
<parameter name="MEM_CLK_FREQ" value="400.0" />
<parameter name="USE_MEM_CLK_FREQ" value="false" />
<parameter name="FORCE_DQS_TRACKING" value="AUTO" />
<parameter name="FORCE_SHADOW_REGS" value="AUTO" />
<parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
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<parameter name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" />
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<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
<parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
<parameter name="DEVICE_FAMILY_PARAM" value="" />
<parameter name="SPEED_GRADE" value="7" />
<parameter name="IS_ES_DEVICE" value="false" />
<parameter name="DISABLE_CHILD_MESSAGING" value="false" />
<parameter name="HARD_EMIF" value="true" />
<parameter name="HHP_HPS" value="true" />
<parameter name="HHP_HPS_VERIFICATION" value="false" />
<parameter name="HHP_HPS_SIMULATION" value="false" />
<parameter name="HPS_PROTOCOL" value="DDR3" />
<parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
<parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
<parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
<parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
<parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
<parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
<parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
<parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
<parameter name="DLL_SHARING_MODE" value="None" />
<parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
<parameter name="OCT_SHARING_MODE" value="None" />
<parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
<parameter name="MPU_EVENTS_Enable" value="false" />
<parameter name="GP_Enable" value="false" />
<parameter name="DEBUGAPB_Enable" value="false" />
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<parameter name="STM_Enable" value="false" />
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<parameter name="CTI_Enable" value="false" />
<parameter name="TPIUFPGA_Enable" value="false" />
<parameter name="BOOTFROMFPGA_Enable" value="false" />
<parameter name="TEST_Enable" value="false" />
<parameter name="HLGPI_Enable" value="false" />
<parameter name="BSEL_EN" value="false" />
<parameter name="BSEL" value="1" />
<parameter name="CSEL_EN" value="false" />
<parameter name="CSEL" value="0" />
<parameter name="F2S_Width" value="2" />
<parameter name="S2F_Width" value="2" />
<parameter name="LWH2F_Enable" value="true" />
<parameter name="F2SDRAM_Type">Avalon-MM Bidirectional</parameter>
<parameter name="F2SDRAM_Width" value="64" />
<parameter name="BONDING_OUT_ENABLED" value="false" />
<parameter name="S2FCLK_COLDRST_Enable" value="false" />
<parameter name="S2FCLK_PENDINGRST_Enable" value="false" />
<parameter name="F2SCLK_DBGRST_Enable" value="false" />
<parameter name="F2SCLK_WARMRST_Enable" value="false" />
<parameter name="F2SCLK_COLDRST_Enable" value="false" />
<parameter name="DMA_Enable">No,No,No,No,No,No,No,No</parameter>
<parameter name="F2SINTERRUPT_Enable" value="true" />
<parameter name="S2FINTERRUPT_CAN_Enable" value="false" />
<parameter name="S2FINTERRUPT_CLOCKPERIPHERAL_Enable" value="false" />
<parameter name="S2FINTERRUPT_CTI_Enable" value="false" />
<parameter name="S2FINTERRUPT_DMA_Enable" value="false" />
<parameter name="S2FINTERRUPT_EMAC_Enable" value="false" />
<parameter name="S2FINTERRUPT_FPGAMANAGER_Enable" value="false" />
<parameter name="S2FINTERRUPT_GPIO_Enable" value="false" />
<parameter name="S2FINTERRUPT_I2CEMAC_Enable" value="false" />
<parameter name="S2FINTERRUPT_I2CPERIPHERAL_Enable" value="false" />
<parameter name="S2FINTERRUPT_L4TIMER_Enable" value="false" />
<parameter name="S2FINTERRUPT_NAND_Enable" value="false" />
<parameter name="S2FINTERRUPT_OSCTIMER_Enable" value="false" />
<parameter name="S2FINTERRUPT_QSPI_Enable" value="false" />
<parameter name="S2FINTERRUPT_SDMMC_Enable" value="false" />
<parameter name="S2FINTERRUPT_SPIMASTER_Enable" value="false" />
<parameter name="S2FINTERRUPT_SPISLAVE_Enable" value="false" />
<parameter name="S2FINTERRUPT_UART_Enable" value="false" />
<parameter name="S2FINTERRUPT_USB_Enable" value="false" />
<parameter name="S2FINTERRUPT_WATCHDOG_Enable" value="false" />
<parameter name="EMAC0_PinMuxing" value="Unused" />
<parameter name="EMAC0_Mode" value="N/A" />
<parameter name="EMAC1_PinMuxing" value="HPS I/O Set 0" />
<parameter name="EMAC1_Mode" value="RGMII" />
<parameter name="NAND_PinMuxing" value="Unused" />
<parameter name="NAND_Mode" value="N/A" />
<parameter name="QSPI_PinMuxing" value="HPS I/O Set 0" />
<parameter name="QSPI_Mode" value="1 SS" />
<parameter name="SDIO_PinMuxing" value="HPS I/O Set 0" />
<parameter name="SDIO_Mode" value="4-bit Data" />
<parameter name="USB0_PinMuxing" value="Unused" />
<parameter name="USB0_Mode" value="N/A" />
<parameter name="USB1_PinMuxing" value="HPS I/O Set 0" />
<parameter name="USB1_Mode" value="SDR" />
<parameter name="SPIM0_PinMuxing" value="FPGA" />
<parameter name="SPIM0_Mode" value="Full" />
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<parameter name="SPIM1_PinMuxing" value="HPS I/O Set 0" />
<parameter name="SPIM1_Mode" value="Single Slave Select" />
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<parameter name="SPIS0_PinMuxing" value="Unused" />
<parameter name="SPIS0_Mode" value="N/A" />
<parameter name="SPIS1_PinMuxing" value="Unused" />
<parameter name="SPIS1_Mode" value="N/A" />
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<parameter name="UART0_PinMuxing" value="HPS I/O Set 0" />
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<parameter name="UART0_Mode" value="No Flow Control" />
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<parameter name="UART1_PinMuxing" value="Unused" />
<parameter name="UART1_Mode" value="N/A" />
<parameter name="I2C0_PinMuxing" value="Unused" />
<parameter name="I2C0_Mode" value="N/A" />
c5soc: initial a5soc copy
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<parameter name="I2C1_PinMuxing" value="Unused" />
<parameter name="I2C1_Mode" value="N/A" />
<parameter name="I2C2_PinMuxing" value="Unused" />
<parameter name="I2C2_Mode" value="N/A" />
<parameter name="I2C3_PinMuxing" value="Unused" />
<parameter name="I2C3_Mode" value="N/A" />
<parameter name="CAN0_PinMuxing" value="Unused" />
<parameter name="CAN0_Mode" value="N/A" />
<parameter name="CAN1_PinMuxing" value="Unused" />
<parameter name="CAN1_Mode" value="N/A" />
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<parameter name="TRACE_PinMuxing" value="Unused" />
<parameter name="TRACE_Mode" value="N/A" />
<parameter name="GPIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
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<parameter name="LOANIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
<parameter name="S2FCLK_USER0CLK_Enable" value="true" />
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<parameter name="S2FCLK_USER0CLK_FREQ" value="100" />
c5soc: initial a5soc copy
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<parameter name="S2FCLK_USER1CLK_Enable" value="false" />
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<parameter name="S2FCLK_USER1CLK_FREQ" value="100" />
c5soc: initial a5soc copy
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<parameter name="S2FCLK_USER2CLK_Enable" value="false" />
<parameter name="S2FCLK_USER2CLK_FREQ" value="100" />
<parameter name="F2SCLK_PERIPHCLK_Enable" value="false" />
<parameter name="F2SCLK_PERIPHCLK_FREQ" value="100" />
<parameter name="F2SCLK_SDRAMCLK_Enable" value="false" />
<parameter name="F2SCLK_SDRAMCLK_FREQ" value="100" />
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<parameter name="F2H_AXI_CLOCK_FREQ" value="50000000" />
<parameter name="H2F_AXI_CLOCK_FREQ" value="50000000" />
<parameter name="H2F_LW_AXI_CLOCK_FREQ" value="50000000" />
<parameter name="F2H_SDRAM0_CLOCK_FREQ" value="100000000" />
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<parameter name="F2H_SDRAM1_CLOCK_FREQ" value="100" />
<parameter name="F2H_SDRAM2_CLOCK_FREQ" value="100" />
<parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
<parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
<parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
<parameter name="H2F_CTI_CLOCK_FREQ" value="100" />
<parameter name="H2F_TPIU_CLOCK_IN_FREQ" value="100" />
<parameter name="H2F_DEBUG_APB_CLOCK_FREQ" value="100" />
<parameter
name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
value="100" />
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN" value="100" />
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN" value="100" />
<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK" value="100" />
<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK" value="100" />
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN" value="100" />
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN" value="100" />
<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK" value="100" />
<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK" value="100" />
<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT" value="100" />
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SDIO_CLK_IN" value="100" />
<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK" value="100" />
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN" value="100" />
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN" value="100" />
<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="100" />
<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" />
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN" value="100" />
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN" value="100" />
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="100" />
<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK" value="100" />
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN" value="100" />
<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK" value="100" />
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN" value="100" />
<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK" value="100" />
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN" value="100" />
<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK" value="100" />
fmcomms2/c5soc: initial checkin
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<parameter name="device_name" value="5CSXFC6D6F31C8ES" />
c5soc: initial a5soc copy
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<parameter
name="quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces"
value="false" />
<parameter
name="quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface"
value="false" />
<parameter name="quartus_ini_hps_ip_enable_test_interface" value="false" />
<parameter name="quartus_ini_hps_ip_fast_f2sdram_sim_model" value="false" />
<parameter name="quartus_ini_hps_ip_suppress_sdram_synth" value="false" />
<parameter
name="quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces"
value="false" />
<parameter name="quartus_ini_hps_ip_enable_bsel_csel" value="false" />
<parameter name="quartus_ini_hps_ip_f2sdram_bonding_out" value="false" />
</module>
<module
kind="altera_avalon_onchip_memory2"
version="13.1"
enabled="1"
name="sys_int_mem">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="blockType" value="AUTO" />
<parameter name="dataWidth" value="64" />
<parameter name="dualPort" value="false" />
<parameter name="initMemContent" value="true" />
<parameter name="initializationFileName" value="onchip_memory2_0" />
<parameter name="instanceID" value="NONE" />
<parameter name="memorySize" value="65536" />
<parameter name="readDuringWriteMode" value="DONT_CARE" />
<parameter name="simAllowMRAMContentsFile" value="false" />
<parameter name="simMemInitOnlyFilename" value="0" />
<parameter name="singleClockOperation" value="false" />
<parameter name="slave1Latency" value="1" />
<parameter name="slave2Latency" value="1" />
<parameter name="useNonDefaultInitFile" value="false" />
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
<parameter name="ecc_enabled" value="false" />
<parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
fmcomms2/c5soc: initial checkin
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<parameter name="deviceFamily" value="Cyclone V" />
<parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TE
c5soc: initial a5soc copy
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</module>
fmcomms2/c5soc: initial checkin
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<module
kind="altera_avalon_sysid_qsys"
version="13.1"
enabled="1"
name="sys_id">
<parameter name="id" value="-1395322110" />
<parameter name="timestamp" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
c5soc: initial a5soc copy
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</module>
fmcomms2/c5soc: initial checkin
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<module kind="altera_avalon_pio" version="13.1" enabled="1" name="sys_gpio">
<parameter name="bitClearingEdgeCapReg" value="true" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="true" />
<parameter name="direction" value="InOut" />
<parameter name="edgeType" value="ANY" />
<parameter name="generateIRQ" value="true" />
<parameter name="irqType" value="EDGE" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="32" />
<parameter name="clockRate" value="50000000" />
</module>
<module kind="axi_ad9361" version="1.0" enabled="1" name="axi_ad9361">
c5soc: initial a5soc copy
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<parameter name="PCORE_ID" value="0" />
<parameter name="PCORE_DEVICE_TYPE" value="0" />
fmcomms2/c5soc: initial checkin
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<parameter name="PCORE_AXI_ID_WIDTH" value="12" />
<parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="50000000" />
<parameter name="AUTO_DEVICE_CLOCK_CLOCK_RATE" value="0" />
<parameter name="AUTO_DELAY_CLOCK_CLOCK_RATE" value="50000000" />
c5soc: initial a5soc copy
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</module>
fmcomms2/c5soc: initial checkin
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<module kind="axi_dmac" version="1.0" enabled="1" name="axi_dmac_dac">
c5soc: initial a5soc copy
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<parameter name="PCORE_ID" value="0" />
fmcomms2/c5soc: initial checkin
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<parameter name="PCORE_AXI_ID_WIDTH" value="12" />
c5soc: initial a5soc copy
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<parameter name="C_DMA_DATA_WIDTH_SRC" value="64" />
<parameter name="C_DMA_DATA_WIDTH_DEST" value="64" />
<parameter name="C_DMA_LENGTH_WIDTH" value="14" />
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
<parameter name="C_2D_TRANSFER" value="0" />
c5soc: initial a5soc copy
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<parameter name="C_CLKS_ASYNC_REQ_SRC" value="1" />
<parameter name="C_CLKS_ASYNC_SRC_DEST" value="1" />
<parameter name="C_CLKS_ASYNC_DEST_REQ" value="1" />
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
<parameter name="C_AXI_SLICE_DEST" value="1" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
<parameter name="C_AXI_SLICE_SRC" value="0" />
<parameter name="C_SYNC_TRANSFER_START" value="0" />
<parameter name="C_CYCLIC" value="1" />
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
<parameter name="C_DMA_TYPE_DEST" value="2" />
<parameter name="C_DMA_TYPE_SRC" value="0" />
<parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="50000000" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
</module>
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
<module kind="axi_dmac" version="1.0" enabled="1" name="axi_dmac_adc">
<parameter name="PCORE_ID" value="0" />
<parameter name="PCORE_AXI_ID_WIDTH" value="12" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
<parameter name="C_DMA_DATA_WIDTH_SRC" value="64" />
<parameter name="C_DMA_DATA_WIDTH_DEST" value="64" />
<parameter name="C_DMA_LENGTH_WIDTH" value="14" />
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
<parameter name="C_2D_TRANSFER" value="0" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
<parameter name="C_CLKS_ASYNC_REQ_SRC" value="1" />
<parameter name="C_CLKS_ASYNC_SRC_DEST" value="1" />
<parameter name="C_CLKS_ASYNC_DEST_REQ" value="1" />
<parameter name="C_AXI_SLICE_DEST" value="0" />
<parameter name="C_AXI_SLICE_SRC" value="0" />
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
<parameter name="C_SYNC_TRANSFER_START" value="1" />
<parameter name="C_CYCLIC" value="0" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
<parameter name="C_DMA_TYPE_DEST" value="0" />
<parameter name="C_DMA_TYPE_SRC" value="2" />
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
<parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="50000000" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
</module>
<connection
kind="clock"
version="13.1"
start="sys_clk.clk"
end="sys_hps.f2h_axi_clock" />
<connection
kind="avalon"
version="13.1"
start="sys_hps.h2f_axi_master"
end="sys_int_mem.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="clock"
version="13.1"
start="sys_clk.clk"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
end="sys_hps.h2f_lw_axi_clock" />
<connection kind="clock" version="13.1" start="sys_clk.clk" end="sys_id.clk" />
c5soc: initial a5soc copy
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<connection
kind="reset"
version="13.1"
start="sys_clk.clk_reset"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
end="sys_id.reset" />
c5soc: initial a5soc copy
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<connection
kind="avalon"
version="13.1"
start="sys_hps.h2f_lw_axi_master"
fmcomms2/c5soc: initial checkin
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end="sys_id.control_slave">
c5soc: initial a5soc copy
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<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010000" />
<parameter name="defaultConnection" value="false" />
</connection>
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
<connection kind="clock" version="13.1" start="sys_clk.clk" end="sys_gpio.clk" />
c5soc: initial a5soc copy
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<connection
kind="reset"
version="13.1"
start="sys_clk.clk_reset"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
end="sys_gpio.reset" />
c5soc: initial a5soc copy
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<connection
kind="avalon"
version="13.1"
start="sys_hps.h2f_lw_axi_master"
fmcomms2/c5soc: initial checkin
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end="sys_gpio.s1">
c5soc: initial a5soc copy
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<parameter name="arbitrationPriority" value="1" />
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
<parameter name="baseAddress" value="0x00010080" />
c5soc: initial a5soc copy
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<parameter name="defaultConnection" value="false" />
</connection>
<connection
fmcomms2/c5soc: initial checkin
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kind="interrupt"
c5soc: initial a5soc copy
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version="13.1"
fmcomms2/c5soc: initial checkin
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start="sys_hps.f2h_irq0"
end="sys_gpio.irq">
<parameter name="irqNumber" value="0" />
c5soc: initial a5soc copy
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</connection>
<connection
kind="clock"
version="13.1"
start="sys_clk.clk"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
end="sys_hps.h2f_axi_clock" />
c5soc: initial a5soc copy
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<connection
kind="clock"
version="13.1"
fmcomms2/c5soc: initial checkin
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start="sys_clk.clk"
end="sys_int_mem.clk1" />
c5soc: initial a5soc copy
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<connection
kind="reset"
version="13.1"
start="sys_clk.clk_reset"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
end="sys_int_mem.reset1" />
c5soc: initial a5soc copy
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<connection
kind="clock"
version="13.1"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
start="sys_clk.clk"
end="axi_ad9361.s_axi_clock" />
c5soc: initial a5soc copy
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<connection
kind="reset"
version="13.1"
start="sys_clk.clk_reset"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
end="axi_ad9361.s_axi_reset" />
c5soc: initial a5soc copy
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<connection
kind="avalon"
version="13.1"
start="sys_hps.h2f_lw_axi_master"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
end="axi_ad9361.s_axi">
c5soc: initial a5soc copy
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<parameter name="arbitrationPriority" value="1" />
AD9361: Altera, modified address width so that all registers are accessible Modified qsys project with the new address span
2014-07-08 07:41:51 +00:00
<parameter name="baseAddress" value="0x00020000" />
c5soc: initial a5soc copy
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<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="clock"
version="13.1"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
start="sys_clk.clk"
end="axi_ad9361.delay_clock" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
<connection
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
kind="clock"
c5soc: initial a5soc copy
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version="13.1"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
start="sys_hps.h2f_user0_clock"
end="sys_hps.f2h_sdram0_clock" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
<connection
kind="clock"
version="13.1"
start="sys_clk.clk"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
end="axi_dmac_dac.s_axi_clock" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
<connection
kind="reset"
version="13.1"
start="sys_clk.clk_reset"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
end="axi_dmac_dac.s_axi_reset" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
<connection
kind="avalon"
version="13.1"
start="sys_hps.h2f_lw_axi_master"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
end="axi_dmac_dac.s_axi">
c5soc: initial a5soc copy
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<parameter name="arbitrationPriority" value="1" />
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
<parameter name="baseAddress" value="0x4000" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="clock"
version="13.1"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
start="sys_hps.h2f_user0_clock"
end="axi_dmac_dac.m_src_axi_clock" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
<connection
kind="reset"
version="13.1"
start="sys_clk.clk_reset"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
end="axi_dmac_dac.m_src_axi_reset" />
c5soc: initial a5soc copy
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<connection
kind="avalon"
version="13.1"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
start="axi_dmac_dac.m_src_axi"
end="sys_hps.f2h_sdram0_data">
c5soc: initial a5soc copy
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<parameter name="arbitrationPriority" value="1" />
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
<parameter name="baseAddress" value="0x0000" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="clock"
version="13.1"
start="sys_clk.clk"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
end="axi_dmac_adc.s_axi_clock" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
<connection
kind="reset"
version="13.1"
start="sys_clk.clk_reset"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
end="axi_dmac_adc.s_axi_reset" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
<connection
kind="avalon"
version="13.1"
start="sys_hps.h2f_lw_axi_master"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
end="axi_dmac_adc.s_axi">
c5soc: initial a5soc copy
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<parameter name="arbitrationPriority" value="1" />
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
<parameter name="baseAddress" value="0x0000" />
c5soc: initial a5soc copy
2014-07-01 17:09:38 +00:00
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="clock"
version="13.1"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
start="sys_hps.h2f_user0_clock"
end="axi_dmac_adc.m_dest_axi_clock" />
c5soc: initial a5soc copy
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<connection
kind="reset"
version="13.1"
start="sys_clk.clk_reset"
fmcomms2/c5soc: initial checkin
2014-07-02 18:56:00 +00:00
end="axi_dmac_adc.m_dest_axi_reset" />
c5soc: initial a5soc copy
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<connection
kind="avalon"
version="13.1"
fmcomms2/c5soc: initial checkin
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start="axi_dmac_adc.m_dest_axi"
c5soc: initial a5soc copy
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end="sys_hps.f2h_sdram0_data">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
fmcomms2/c5soc: initial checkin
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kind="interrupt"
c5soc: initial a5soc copy
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version="13.1"
fmcomms2/c5soc: initial checkin
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start="sys_hps.f2h_irq0"
end="axi_dmac_dac.interrupt_sender">
<parameter name="irqNumber" value="1" />
c5soc: initial a5soc copy
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</connection>
<connection
kind="interrupt"
version="13.1"
start="sys_hps.f2h_irq0"
fmcomms2/c5soc: initial checkin
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end="axi_dmac_adc.interrupt_sender">
<parameter name="irqNumber" value="2" />
c5soc: initial a5soc copy
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</connection>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
fmcomms2/c5soc: initial checkin
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<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
c5soc: initial a5soc copy
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</system>