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pluto_hdl_adi/projects/adrv9371x/a10soc/system_constr.sdc

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Add copyright and license to .sdc files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-10 08:36:06 +00:00
###############################################################################
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
adrv9371x- added
2016-05-20 15:46:25 +00:00
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
ad9371x/intel: Fix fPLL configuration When phase alignment is active, the PFD frequency value should be used as outclk1 actual frequency. The configuration interface of the fPLL does not support fractional values. If the reference clock is fractional, the tool will throw an error that requirement above is not respected. Round up the reference clock for the SERDES and the lane rate in order to overcome this issue, until it's not fixed by Intel.
2021-01-05 09:15:00 +00:00
create_clock -period "8.1300813 ns" -name ref_clk0 [get_ports {ref_clk0}]
create_clock -period "8.1300813 ns" -name ref_clk1 [get_ports {ref_clk1}]
adrv9371x- added
2016-05-20 15:46:25 +00:00
derive_pll_clocks
derive_clock_uncertainty
adrv9371x/a10soc: Fix constraints Signed-off-by: Istvan Csomortani <istvan.csomortani@analog.com>
2017-05-02 11:30:19 +00:00
set_false_path -to [get_registers *sys_gpio_bd|readdata[12]*]
set_false_path -to [get_registers *sys_gpio_bd|readdata[13]*]
adrv9371x/a10soc- altera reset synchronizer false path?
2017-03-23 13:44:18 +00:00
set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]