pluto_hdl_adi/library/Makefile

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2015-04-01 20:26:23 +00:00
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
include ../quiet.mk
.PHONY: all lib clean clean-all
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all: lib
clean:
$(MAKE) -C axi_ad5766 clean
$(MAKE) -C axi_ad6676 clean
$(MAKE) -C axi_ad7616 clean
$(MAKE) -C axi_ad9122 clean
$(MAKE) -C axi_ad9144 clean
$(MAKE) -C axi_ad9152 clean
$(MAKE) -C axi_ad9162 clean
$(MAKE) -C axi_ad9250 clean
$(MAKE) -C axi_ad9265 clean
$(MAKE) -C axi_ad9361 clean
$(MAKE) -C axi_ad9371 clean
$(MAKE) -C axi_ad9434 clean
$(MAKE) -C axi_ad9467 clean
$(MAKE) -C axi_ad9625 clean
$(MAKE) -C axi_ad9671 clean
$(MAKE) -C axi_ad9680 clean
$(MAKE) -C axi_ad9684 clean
$(MAKE) -C axi_ad9739a clean
$(MAKE) -C axi_ad9963 clean
$(MAKE) -C axi_adc_decimate clean
$(MAKE) -C axi_adc_trigger clean
$(MAKE) -C axi_adrv9009 clean
$(MAKE) -C axi_clkgen clean
$(MAKE) -C axi_dac_interpolate clean
$(MAKE) -C axi_dmac clean
$(MAKE) -C axi_fan_control clean
$(MAKE) -C axi_fmcadc5_sync clean
$(MAKE) -C axi_generic_adc clean
$(MAKE) -C axi_gpreg clean
$(MAKE) -C axi_hdmi_rx clean
$(MAKE) -C axi_hdmi_tx clean
$(MAKE) -C axi_i2s_adi clean
$(MAKE) -C axi_intr_monitor clean
axi_laser_driver: Initial commit The laser driver contains the axi_pulse_gen's IP and an additional register map which controls/monitor the laser driver enable control line and the over temperature warning line (OTW). It also contains an interrupt logic, which allows to generate an interrupt in function of the generated pulse or incoming OTW signal. The IPs register maps looks as follow: 0x00 - axi_pulse_gen register map 0x80 - axi_laser_driver register map 0x80 - DRIVER_ENABLE 0x84 - DRIVER_OTW 0x88 - EXT_CLK_COUNTER 0xA0 - IRQ_MASK 0xA4 - IRQ_SOURCE 0xA8 - IRQ_PENDING 0xAC - SEQUENCER_CONTROL 0 - SEQUENCER_ENABLE 1 - AUTO_SEQUENCER_ENABLED 0xB0 - SEQUENCER_SYNC_OFFSET 0xB4 - AUTO_SEQUENCE [ 1: 0] - CHANNEL_SEL_0 [ 5: 4] - CHANNEL_SEL_1 [ 9: 8] - CHANNEL_SEL_2 [13:12] - CHANNEL_SEL_3 0xB8 - MANUAL_SEQUENCE [ 1: 0] - MANUAL_CHANNEL_SEL Current interrupt sources scheme is: - bit 0 : pulse (triggered by the level of the pulse) - bit 1 : OTW_N enter (triggered by positive edge of the OTW_N) - bit 2 : OTW_N exit (triggered by the level of the pulse) Generate a reset signal before the pulse which can be used to reset various IP's of the data path (eg. pack/cpack). This can help to clear out the internal buffers and registers of these IP, starting clean at the moment when the actual pulse arrives. The sequencer has an auto and a manual mode, and can be set to custom sequences of the TIA channel selection lines sate. The sequencer in auto mode is synchronized to the pulse, it will change its state before a generated pulse which will drive the lasers. The offset between the sequencer beat and the laser driver pulse can be modified through an AXI register.
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$(MAKE) -C axi_laser_driver clean
$(MAKE) -C axi_logic_analyzer clean
$(MAKE) -C axi_mc_controller clean
$(MAKE) -C axi_mc_current_monitor clean
$(MAKE) -C axi_mc_speed clean
$(MAKE) -C axi_pulse_gen clean
$(MAKE) -C axi_rd_wr_combiner clean
$(MAKE) -C axi_spdif_rx clean
$(MAKE) -C axi_spdif_tx clean
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$(MAKE) -C axi_sysid clean
$(MAKE) -C axi_usb_fx3 clean
$(MAKE) -C cn0363/cn0363_dma_sequencer clean
$(MAKE) -C cn0363/cn0363_phase_data_sync clean
$(MAKE) -C cordic_demod clean
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$(MAKE) -C intel/adi_jesd204 clean
$(MAKE) -C intel/avl_adxcfg clean
$(MAKE) -C intel/avl_adxcvr clean
$(MAKE) -C intel/avl_adxcvr_octet_swap clean
$(MAKE) -C intel/avl_adxphy clean
$(MAKE) -C intel/avl_dacfifo clean
$(MAKE) -C intel/axi_adxcvr clean
$(MAKE) -C intel/common/intel_mem_asym clean
$(MAKE) -C intel/common/intel_serdes clean
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$(MAKE) -C intel/jesd204_phy clean
$(MAKE) -C intel/util_clkdiv clean
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$(MAKE) -C jesd204/ad_ip_jesd204_tpl_adc clean
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$(MAKE) -C jesd204/ad_ip_jesd204_tpl_dac clean
$(MAKE) -C jesd204/axi_jesd204_common clean
$(MAKE) -C jesd204/axi_jesd204_rx clean
$(MAKE) -C jesd204/axi_jesd204_tx clean
$(MAKE) -C jesd204/jesd204_common clean
$(MAKE) -C jesd204/jesd204_rx clean
$(MAKE) -C jesd204/jesd204_rx_static_config clean
$(MAKE) -C jesd204/jesd204_soft_pcs_rx clean
$(MAKE) -C jesd204/jesd204_soft_pcs_tx clean
$(MAKE) -C jesd204/jesd204_tx clean
$(MAKE) -C jesd204/jesd204_tx_static_config clean
$(MAKE) -C spi_engine/axi_spi_engine clean
$(MAKE) -C spi_engine/spi_engine_execution clean
$(MAKE) -C spi_engine/spi_engine_interconnect clean
$(MAKE) -C spi_engine/spi_engine_offload clean
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$(MAKE) -C sysid_rom clean
$(MAKE) -C util_adcfifo clean
$(MAKE) -C util_axis_fifo clean
$(MAKE) -C util_axis_resize clean
$(MAKE) -C util_axis_upscale clean
$(MAKE) -C util_bsplit clean
$(MAKE) -C util_cdc clean
$(MAKE) -C util_cic clean
$(MAKE) -C util_dacfifo clean
$(MAKE) -C util_dec256sinc24b clean
$(MAKE) -C util_delay clean
$(MAKE) -C util_extract clean
$(MAKE) -C util_fir_dec clean
$(MAKE) -C util_fir_int clean
$(MAKE) -C util_gmii_to_rgmii clean
$(MAKE) -C util_i2c_mixer clean
$(MAKE) -C util_mfifo clean
$(MAKE) -C util_pack/util_cpack2 clean
Add util_upack2 core The util_upack2 core is similar to the util_upack core. It unpacks, or deinterleaves, a data stream onto multiple ports. The upack2 core uses a streaming AXI interface for its data source instead of a FIFO interface like the upack core uses. On the output side the upack2 core uses a multi-port FIFO interface. There is a single data request signal (fifo_rd_en) for all ports. But each port can be individually enabled or disabled using the enable signals. This modified architecture allows the upack2 core to better generate the valid and underflow control signals to indicate whether data is available in a response to a data request. If fifo_rd_en is asserted and data is available the fifo_rd_valid signal are asserted in the following clock cycle. The enabled fifo_rd_data ports will be contain valid data during the same clock cycle as fifo_rd_valid is asserted. During other clock cycles the output data is undefined. On disabled ports the data is always undefined. If no data is available instead the fifo_rd_underflow signal is asserted in the following clock cycle and the output of all fifo_rd_data ports is undefined. This core is build using the common pack infrastructure. The core that is specific to the upack2 core is mainly only responsible for generating the control signals for the external interfaces. The core is accompanied by a test bench that verifies correct behavior for all possible combinations of enable masks. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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$(MAKE) -C util_pack/util_upack2 clean
$(MAKE) -C util_pulse_gen clean
$(MAKE) -C util_rfifo clean
$(MAKE) -C util_sigma_delta_spi clean
$(MAKE) -C util_tdd_sync clean
$(MAKE) -C util_var_fifo clean
$(MAKE) -C util_wfifo clean
$(MAKE) -C xilinx/axi_adcfifo clean
$(MAKE) -C xilinx/axi_adxcvr clean
$(MAKE) -C xilinx/axi_dacfifo clean
$(MAKE) -C xilinx/axi_xcvrlb clean
$(MAKE) -C xilinx/util_adxcvr clean
$(MAKE) -C xilinx/util_clkdiv clean
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$(MAKE) -C interfaces clean
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clean-all:clean
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lib:
$(MAKE) -C axi_ad5766
$(MAKE) -C axi_ad6676
$(MAKE) -C axi_ad7616
$(MAKE) -C axi_ad9122
$(MAKE) -C axi_ad9144
$(MAKE) -C axi_ad9152
$(MAKE) -C axi_ad9162
$(MAKE) -C axi_ad9250
$(MAKE) -C axi_ad9265
$(MAKE) -C axi_ad9361
$(MAKE) -C axi_ad9371
$(MAKE) -C axi_ad9434
$(MAKE) -C axi_ad9467
$(MAKE) -C axi_ad9625
$(MAKE) -C axi_ad9671
$(MAKE) -C axi_ad9680
$(MAKE) -C axi_ad9684
$(MAKE) -C axi_ad9739a
$(MAKE) -C axi_ad9963
$(MAKE) -C axi_adc_decimate
$(MAKE) -C axi_adc_trigger
$(MAKE) -C axi_adrv9009
$(MAKE) -C axi_clkgen
$(MAKE) -C axi_dac_interpolate
$(MAKE) -C axi_dmac
$(MAKE) -C axi_fan_control
$(MAKE) -C axi_fmcadc5_sync
$(MAKE) -C axi_generic_adc
$(MAKE) -C axi_gpreg
$(MAKE) -C axi_hdmi_rx
$(MAKE) -C axi_hdmi_tx
$(MAKE) -C axi_i2s_adi
$(MAKE) -C axi_intr_monitor
axi_laser_driver: Initial commit The laser driver contains the axi_pulse_gen's IP and an additional register map which controls/monitor the laser driver enable control line and the over temperature warning line (OTW). It also contains an interrupt logic, which allows to generate an interrupt in function of the generated pulse or incoming OTW signal. The IPs register maps looks as follow: 0x00 - axi_pulse_gen register map 0x80 - axi_laser_driver register map 0x80 - DRIVER_ENABLE 0x84 - DRIVER_OTW 0x88 - EXT_CLK_COUNTER 0xA0 - IRQ_MASK 0xA4 - IRQ_SOURCE 0xA8 - IRQ_PENDING 0xAC - SEQUENCER_CONTROL 0 - SEQUENCER_ENABLE 1 - AUTO_SEQUENCER_ENABLED 0xB0 - SEQUENCER_SYNC_OFFSET 0xB4 - AUTO_SEQUENCE [ 1: 0] - CHANNEL_SEL_0 [ 5: 4] - CHANNEL_SEL_1 [ 9: 8] - CHANNEL_SEL_2 [13:12] - CHANNEL_SEL_3 0xB8 - MANUAL_SEQUENCE [ 1: 0] - MANUAL_CHANNEL_SEL Current interrupt sources scheme is: - bit 0 : pulse (triggered by the level of the pulse) - bit 1 : OTW_N enter (triggered by positive edge of the OTW_N) - bit 2 : OTW_N exit (triggered by the level of the pulse) Generate a reset signal before the pulse which can be used to reset various IP's of the data path (eg. pack/cpack). This can help to clear out the internal buffers and registers of these IP, starting clean at the moment when the actual pulse arrives. The sequencer has an auto and a manual mode, and can be set to custom sequences of the TIA channel selection lines sate. The sequencer in auto mode is synchronized to the pulse, it will change its state before a generated pulse which will drive the lasers. The offset between the sequencer beat and the laser driver pulse can be modified through an AXI register.
2019-03-19 12:05:14 +00:00
$(MAKE) -C axi_laser_driver
$(MAKE) -C axi_logic_analyzer
$(MAKE) -C axi_mc_controller
$(MAKE) -C axi_mc_current_monitor
$(MAKE) -C axi_mc_speed
$(MAKE) -C axi_pulse_gen
$(MAKE) -C axi_rd_wr_combiner
$(MAKE) -C axi_spdif_rx
$(MAKE) -C axi_spdif_tx
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$(MAKE) -C axi_sysid
$(MAKE) -C axi_usb_fx3
$(MAKE) -C cn0363/cn0363_dma_sequencer
$(MAKE) -C cn0363/cn0363_phase_data_sync
$(MAKE) -C cordic_demod
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$(MAKE) -C intel/adi_jesd204
$(MAKE) -C intel/avl_adxcfg
$(MAKE) -C intel/avl_adxcvr
$(MAKE) -C intel/avl_adxcvr_octet_swap
$(MAKE) -C intel/avl_adxphy
$(MAKE) -C intel/avl_dacfifo
$(MAKE) -C intel/axi_adxcvr
$(MAKE) -C intel/common/intel_mem_asym
$(MAKE) -C intel/common/intel_serdes
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$(MAKE) -C intel/jesd204_phy
$(MAKE) -C intel/util_clkdiv
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$(MAKE) -C jesd204/ad_ip_jesd204_tpl_adc
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$(MAKE) -C jesd204/ad_ip_jesd204_tpl_dac
$(MAKE) -C jesd204/axi_jesd204_common
$(MAKE) -C jesd204/axi_jesd204_rx
$(MAKE) -C jesd204/axi_jesd204_tx
$(MAKE) -C jesd204/jesd204_common
$(MAKE) -C jesd204/jesd204_rx
$(MAKE) -C jesd204/jesd204_rx_static_config
$(MAKE) -C jesd204/jesd204_soft_pcs_rx
$(MAKE) -C jesd204/jesd204_soft_pcs_tx
$(MAKE) -C jesd204/jesd204_tx
$(MAKE) -C jesd204/jesd204_tx_static_config
$(MAKE) -C spi_engine/axi_spi_engine
$(MAKE) -C spi_engine/spi_engine_execution
$(MAKE) -C spi_engine/spi_engine_interconnect
$(MAKE) -C spi_engine/spi_engine_offload
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$(MAKE) -C sysid_rom
$(MAKE) -C util_adcfifo
$(MAKE) -C util_axis_fifo
$(MAKE) -C util_axis_resize
$(MAKE) -C util_axis_upscale
$(MAKE) -C util_bsplit
$(MAKE) -C util_cdc
$(MAKE) -C util_cic
$(MAKE) -C util_dacfifo
$(MAKE) -C util_dec256sinc24b
$(MAKE) -C util_delay
$(MAKE) -C util_extract
$(MAKE) -C util_fir_dec
$(MAKE) -C util_fir_int
$(MAKE) -C util_gmii_to_rgmii
$(MAKE) -C util_i2c_mixer
$(MAKE) -C util_mfifo
$(MAKE) -C util_pack/util_cpack2
Add util_upack2 core The util_upack2 core is similar to the util_upack core. It unpacks, or deinterleaves, a data stream onto multiple ports. The upack2 core uses a streaming AXI interface for its data source instead of a FIFO interface like the upack core uses. On the output side the upack2 core uses a multi-port FIFO interface. There is a single data request signal (fifo_rd_en) for all ports. But each port can be individually enabled or disabled using the enable signals. This modified architecture allows the upack2 core to better generate the valid and underflow control signals to indicate whether data is available in a response to a data request. If fifo_rd_en is asserted and data is available the fifo_rd_valid signal are asserted in the following clock cycle. The enabled fifo_rd_data ports will be contain valid data during the same clock cycle as fifo_rd_valid is asserted. During other clock cycles the output data is undefined. On disabled ports the data is always undefined. If no data is available instead the fifo_rd_underflow signal is asserted in the following clock cycle and the output of all fifo_rd_data ports is undefined. This core is build using the common pack infrastructure. The core that is specific to the upack2 core is mainly only responsible for generating the control signals for the external interfaces. The core is accompanied by a test bench that verifies correct behavior for all possible combinations of enable masks. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-07 12:39:27 +00:00
$(MAKE) -C util_pack/util_upack2
$(MAKE) -C util_pulse_gen
$(MAKE) -C util_rfifo
$(MAKE) -C util_sigma_delta_spi
$(MAKE) -C util_tdd_sync
$(MAKE) -C util_var_fifo
$(MAKE) -C util_wfifo
$(MAKE) -C xilinx/axi_adcfifo
$(MAKE) -C xilinx/axi_adxcvr
$(MAKE) -C xilinx/axi_dacfifo
$(MAKE) -C xilinx/axi_xcvrlb
$(MAKE) -C xilinx/util_adxcvr
$(MAKE) -C xilinx/util_clkdiv
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$(MAKE) -C interfaces
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####################################################################################
####################################################################################