83 lines
3.3 KiB
Coq
83 lines
3.3 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// Divides the input clock to SEL_0_DIV if clk_sel is 0 or SEL_1_DIV if
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// clk_sel is 1. Provides a glitch free output clock
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// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_clkdiv_alt #(
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parameter SIM_DEVICE = "CYCLONE5",
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parameter CLOCK_TYPE = "Global Clock") (
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input clk,
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input reset,
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output clk_out,
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output reset_out
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);
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reg enable;
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reg reset_d1;
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assign reset_out = reset | reset_d1;
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always @(posedge clk) begin
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reset_d1 <= reset;
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end
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always @(posedge clk) begin
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enable <= ~enable;
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end
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generate if (SIM_DEVICE == "CYCLONE5") begin
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cyclonev_clkena #(
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.clock_type ("Global Clock"),
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.ena_register_mode ("falling edge"),
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.lpm_type ("cyclonev_clkena")
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) clock_divider_by_2 (
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.ena(enable),
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.enaout(),
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.inclk(clk),
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// .clkselect (2'b0),
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.outclk(clk_out));
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end endgenerate
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endmodule // util_clkdiv_alt
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