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pluto_hdl_adi/library/util_tdd_sync/Makefile

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util_tdd_sync: Initial commit A synchronization signal generator for AD9361 running on TDD mode. If the associated device is master, the module generates a pulse in a defined interval. Otherwise receives the sync signal from outside.
2015-11-11 08:46:11 +00:00
####################################################################################
Makefiles: Update header with the appropriate license
2021-09-15 15:03:11 +00:00
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
util_tdd_sync: Initial commit A synchronization signal generator for AD9361 running on TDD mode. If the associated device is master, the module generates a pulse in a defined interval. Otherwise receives the sync signal from outside.
2015-11-11 08:46:11 +00:00
## Auto-generated, do not modify!
####################################################################################
Regenerate library Makefiles using the new shared Makefile include This reduces the amount of boilerplate code that is present in these Makefiles by a lot. It also makes it possible to update the Makefile rules in future without having to re-generate all the Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-23 09:19:51 +00:00
LIBRARY_NAME := util_tdd_sync
util_tdd_sync: Initial commit A synchronization signal generator for AD9361 running on TDD mode. If the associated device is master, the module generates a pulse in a defined interval. Otherwise receives the sync signal from outside.
2015-11-11 08:46:11 +00:00
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
GENERIC_DEPS += ../common/util_pulse_gen.v
GENERIC_DEPS += util_tdd_sync.v
XILINX_DEPS += util_tdd_sync_constr.xdc
XILINX_DEPS += util_tdd_sync_ip.tcl
util_tdd_sync: Initial commit A synchronization signal generator for AD9361 running on TDD mode. If the associated device is master, the module generates a pulse in a defined interval. Otherwise receives the sync signal from outside.
2015-11-11 08:46:11 +00:00
Regenerate library Makefiles using the new shared Makefile include This reduces the amount of boilerplate code that is present in these Makefiles by a lot. It also makes it possible to update the Makefile rules in future without having to re-generate all the Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-23 09:19:51 +00:00
include ../scripts/library.mk