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pluto_hdl_adi/library/altera/common/up_rst_constr.sdc

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constraints: Split the regmap CDC constraint into separate file
2017-05-23 11:43:31 +00:00
ad_rst: Update the reset synchronizer module For a proper reset synchronization, the asynchronous reset signal should be connected to the reset pins of the two synchronizer flop, and the data input of the first flop should be connected to VCC. In the first stage we're synchronizing just the reset de-assertion, avoiding the scenario when different parts of the design are reseting at different time, causing unwanted behaviours. In the second stage we're synchronizing the reset assertion. The module expects an ACTIVE_HIGH input reset signal, and provides an ACTIVE_LOW (rstn) and an ACTIVE_HIGH (rst) synchronized reset output signal.
2018-07-18 14:15:20 +00:00
set_false_path -from [get_registers *up_*rst_async*] -to [get_registers *ad_rst:i_core_rst_reg|rst_sync_d]
set_false_path -from [get_registers *up_*rst_async*] -to [get_registers *ad_rst:i_core_rst_reg|rstn]
ad_rst: Update SDC constraints of the module The asynchronous set paths of the reset synchronization stage should be treated as false-paths.
2018-08-07 12:30:12 +00:00
set_false_path -from [get_registers *up_core_preset] -to [get_registers *ad_rst:i_core_rst_reg|rst_async_d*]