pluto_hdl_adi/projects/ad4134_fmc/Readme.md

# AD4134 HDL Project

Here are some pointers to help you:
  * [Board Product Page](https://www.analog.com/AD4134)
  * Parts: [24-Bit, 4-Channel Simultaneous Sampling 1.5 MSPS Precision Alias Free ADC](https://www.analog.com/ad4134)
  * Project Doc: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/ad4134
  * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad4134/hdl
  * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all
projects/ad4134_fmc: Initial commit add support * Updated reference design: spi trigger, ODR parameters - enabled ext_clk for PWM to use 96 MHz spi clk - mofified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK - spi offload trigger signal: PWM trigger used * Moved mem_interconnect to hp1 * Added dclkio GPIO * Updated bd SPIE hierarchy, see library/spi_engine.tcl Signed-off-by: laurent-19 <laurentiu.popa@analog.com> 2022-05-06 13:08:39 +00:00			`# AD4134 HDL Project`

			`Here are some pointers to help you:`
			`* [Board Product Page](https://www.analog.com/AD4134)`
			`* Parts: [24-Bit, 4-Channel Simultaneous Sampling 1.5 MSPS Precision Alias Free ADC](https://www.analog.com/ad4134)`
			`* Project Doc: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/ad4134`
			`* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad4134/hdl`
			`* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all`