37 lines
1.4 KiB
Tcl
37 lines
1.4 KiB
Tcl
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## FIFO depth is 4Mb - 250k samples (65k samples per converter)
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set adc_fifo_address_width 13
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source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
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source ../common/dual_ad9208_bd.tcl
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foreach i {0 1} {
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ad_ip_parameter util_adc_${i}_xcvr CONFIG.RX_CLK25_DIV 30
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ad_ip_parameter util_adc_${i}_xcvr CONFIG.CPLL_CFG0 0x1fa
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ad_ip_parameter util_adc_${i}_xcvr CONFIG.CPLL_CFG1 0x2b
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ad_ip_parameter util_adc_${i}_xcvr CONFIG.CPLL_CFG2 0x2
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ad_ip_parameter util_adc_${i}_xcvr CONFIG.CPLL_FBDIV 2
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ad_ip_parameter util_adc_${i}_xcvr CONFIG.GTY4_CH_HSPMUX 0x4040
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ad_ip_parameter util_adc_${i}_xcvr CONFIG.GTY4_PREIQ_FREQ_BST 1
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ad_ip_parameter util_adc_${i}_xcvr CONFIG.GTY4_RTX_BUF_CML_CTRL 0x5
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ad_ip_parameter util_adc_${i}_xcvr CONFIG.GTY4_RXPI_CFG0 0x3002
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ad_ip_parameter util_adc_${i}_xcvr CONFIG.QPLL_REFCLK_DIV 1
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ad_ip_parameter util_adc_${i}_xcvr CONFIG.QPLL_CFG0 0x333c
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ad_ip_parameter util_adc_${i}_xcvr CONFIG.QPLL_CFG4 0x2
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ad_ip_parameter util_adc_${i}_xcvr CONFIG.QPLL_FBDIV 20
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ad_ip_parameter util_adc_${i}_xcvr CONFIG.GTY4_PPF0_CFG 0xB00
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}
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# Set the smart interconnect to use a lower speed switch to meet timing
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set_property -dict [list CONFIG.ADVANCED_PROPERTIES { __view__ { \
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timing { M00_Buffer { AR_SLR_PIPE 1 AW_SLR_PIPE 1 B_SLR_PIPE 1 R_SLR_PIPE 1 W_SLR_PIPE 1 } } \
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clocking { SW0 { ASSOCIATED_CLK aclk1 } } \
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} }] [get_bd_cells axi_mem_interconnect]
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