2016-06-07 16:24:08 +00:00
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2017-10-11 09:52:15 +00:00
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set dac_fifo_name avl_ad9144_fifo
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set dac_fifo_address_width 10
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set dac_data_width 128
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set dac_dma_data_width 128
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2016-06-07 16:24:08 +00:00
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source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
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2017-10-11 09:52:15 +00:00
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source $ad_hdl_dir/projects/common/altera/dacfifo_qsys.tcl
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2016-06-07 16:24:08 +00:00
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source ../common/daq2_qsys.tcl
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2017-10-20 12:45:05 +00:00
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set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src0/sys_ddr3_cntrl_ctrl_amm_0_to_sys_cpu_data_master_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
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set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src1/sys_ddr3_cntrl_ctrl_amm_0_to_sys_cpu_instruction_master_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
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set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src2/sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9680_dma_m_dest_axi_wr_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
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2017-10-23 15:39:58 +00:00
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set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src3/sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9680_dma_m_dest_axi_rd_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
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set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src4/sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9144_dma_m_src_axi_wr_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
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2017-10-20 12:45:05 +00:00
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set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src5/sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9144_dma_m_src_axi_rd_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
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2017-10-23 15:39:58 +00:00
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set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src6/sys_ddr3_cntrl_ctrl_amm_0_to_sys_ethernet_dma_tx_mm_read_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
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set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src7/sys_ddr3_cntrl_ctrl_amm_0_to_sys_ethernet_dma_rx_mm_write_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
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2017-10-20 12:45:05 +00:00
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set_interconnect_requirement {mm_interconnect_0|sys_ddr3_cntrl_ctrl_amm_0_to_sys_ethernet_dma_rx_mm_write_rsp_width_adapter.src/async_fifo_011.in} {qsys_mm.postTransform.pipelineCount} {1}
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2017-10-23 15:39:58 +00:00
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set_interconnect_requirement {mm_interconnect_0|sys_ddr3_cntrl_ctrl_amm_0_to_sys_cpu_instruction_master_rsp_width_adapter.src/crosser_003.in} {qsys_mm.postTransform.pipelineCount} {1}
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set_interconnect_requirement {mm_interconnect_0|sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9680_dma_m_dest_axi_wr_rsp_width_adapter.src/async_fifo_006.in} {qsys_mm.postTransform.pipelineCount} {1}
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set_interconnect_requirement {mm_interconnect_0|sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9680_dma_m_dest_axi_rd_rsp_width_adapter.src/async_fifo_007.in} {qsys_mm.postTransform.pipelineCount} {1}
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set_interconnect_requirement {mm_interconnect_0|sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9144_dma_m_src_axi_wr_rsp_width_adapter.src/async_fifo_008.in} {qsys_mm.postTransform.pipelineCount} {1}
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set_interconnect_requirement {mm_interconnect_0|sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9144_dma_m_src_axi_rd_rsp_width_adapter.src/async_fifo_009.in} {qsys_mm.postTransform.pipelineCount} {1}
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set_interconnect_requirement {mm_interconnect_0|sys_ddr3_cntrl_ctrl_amm_0_to_sys_ethernet_dma_tx_mm_read_rsp_width_adapter.src/async_fifo_010.in} {qsys_mm.postTransform.pipelineCount} {1}
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