2015-07-03 09:55:37 +00:00
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# fmcomms2
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create_bd_port -dir I rx_clk_in_p
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create_bd_port -dir I rx_clk_in_n
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create_bd_port -dir I rx_frame_in_p
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create_bd_port -dir I rx_frame_in_n
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create_bd_port -dir I -from 5 -to 0 rx_data_in_p
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create_bd_port -dir I -from 5 -to 0 rx_data_in_n
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create_bd_port -dir O tx_clk_out_p
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create_bd_port -dir O tx_clk_out_n
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create_bd_port -dir O tx_frame_out_p
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create_bd_port -dir O tx_frame_out_n
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create_bd_port -dir O -from 5 -to 0 tx_data_out_p
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create_bd_port -dir O -from 5 -to 0 tx_data_out_n
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create_bd_port -dir O enable
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create_bd_port -dir O txnrx
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create_bd_port -dir O tdd_enable
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# ad9361 core
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set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361]
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set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9361
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set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma
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set util_dac_unpack [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack]
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set_property -dict [list CONFIG.CHANNELS {4}] $util_dac_unpack
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set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_adc_dma
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set util_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack]
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set_property -dict [list CONFIG.CHANNELS {4}] $util_adc_pack
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# connections
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ad_connect sys_200m_clk axi_ad9361/delay_clk
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ad_connect axi_ad9361_clk axi_ad9361/l_clk
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ad_connect axi_ad9361_clk axi_ad9361/clk
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ad_connect axi_ad9361_clk axi_ad9361_adc_dma/fifo_wr_clk
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ad_connect axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk
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ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p
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ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n
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ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p
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ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n
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ad_connect rx_data_in_p axi_ad9361/rx_data_in_p
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ad_connect rx_data_in_n axi_ad9361/rx_data_in_n
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ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p
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ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n
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ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p
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ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n
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ad_connect tx_data_out_p axi_ad9361/tx_data_out_p
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ad_connect tx_data_out_n axi_ad9361/tx_data_out_n
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ad_connect enable axi_ad9361/enable
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ad_connect txnrx axi_ad9361/txnrx
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ad_connect tdd_enable axi_ad9361/tdd_enable
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ad_connect axi_ad9361_clk util_adc_pack/clk
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ad_connect axi_ad9361/adc_valid_i0 util_adc_pack/chan_valid_0
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ad_connect axi_ad9361/adc_valid_q0 util_adc_pack/chan_valid_1
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ad_connect axi_ad9361/adc_valid_i1 util_adc_pack/chan_valid_2
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ad_connect axi_ad9361/adc_valid_q1 util_adc_pack/chan_valid_3
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ad_connect axi_ad9361/adc_enable_i0 util_adc_pack/chan_enable_0
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ad_connect axi_ad9361/adc_enable_q0 util_adc_pack/chan_enable_1
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ad_connect axi_ad9361/adc_enable_i1 util_adc_pack/chan_enable_2
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ad_connect axi_ad9361/adc_enable_q1 util_adc_pack/chan_enable_3
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ad_connect axi_ad9361/adc_data_i0 util_adc_pack/chan_data_0
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ad_connect axi_ad9361/adc_data_q0 util_adc_pack/chan_data_1
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ad_connect axi_ad9361/adc_data_i1 util_adc_pack/chan_data_2
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ad_connect axi_ad9361/adc_data_q1 util_adc_pack/chan_data_3
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ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
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ad_connect util_adc_pack/dvalid axi_ad9361_adc_dma/fifo_wr_en
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ad_connect util_adc_pack/dsync axi_ad9361_adc_dma/fifo_wr_sync
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ad_connect util_adc_pack/ddata axi_ad9361_adc_dma/fifo_wr_din
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ad_connect axi_ad9361/adc_dovf axi_ad9361_adc_dma/fifo_wr_overflow
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ad_connect axi_ad9361_clk util_dac_unpack/clk
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ad_connect util_dac_unpack/dac_valid_00 axi_ad9361/dac_valid_i0
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ad_connect util_dac_unpack/dac_valid_01 axi_ad9361/dac_valid_q0
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ad_connect util_dac_unpack/dac_valid_02 axi_ad9361/dac_valid_i1
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ad_connect util_dac_unpack/dac_valid_03 axi_ad9361/dac_valid_q1
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ad_connect util_dac_unpack/dac_enable_00 axi_ad9361/dac_enable_i0
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ad_connect util_dac_unpack/dac_enable_01 axi_ad9361/dac_enable_q0
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ad_connect util_dac_unpack/dac_enable_02 axi_ad9361/dac_enable_i1
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ad_connect util_dac_unpack/dac_enable_03 axi_ad9361/dac_enable_q1
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ad_connect util_dac_unpack/dac_data_00 axi_ad9361/dac_data_i0
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ad_connect util_dac_unpack/dac_data_01 axi_ad9361/dac_data_q0
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ad_connect util_dac_unpack/dac_data_02 axi_ad9361/dac_data_i1
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ad_connect util_dac_unpack/dac_data_03 axi_ad9361/dac_data_q1
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ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
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ad_connect util_dac_unpack/dma_data axi_ad9361_dac_dma/fifo_rd_dout
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ad_connect util_dac_unpack/fifo_valid axi_ad9361_dac_dma/fifo_rd_valid
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ad_connect util_dac_unpack/dma_rd axi_ad9361_dac_dma/fifo_rd_en
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ad_connect axi_ad9361/dac_dunf axi_ad9361_dac_dma/fifo_rd_underflow
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# interconnects
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ad_cpu_interconnect 0x79020000 axi_ad9361
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ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma
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ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma
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ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi
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# interrupts
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ad_cpu_interrupt ps-13 mb-12 axi_ad9361_adc_dma/irq
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ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq
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# ila (adc)
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set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_adc]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {8}] $ila_adc
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set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
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set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE2_WIDTH {1}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE3_WIDTH {1}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE4_WIDTH {16}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE5_WIDTH {16}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE6_WIDTH {16}] $ila_adc
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set_property -dict [list CONFIG.C_PROBE7_WIDTH {16}] $ila_adc
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p_sys_wfifo [current_bd_instance .] sys_wfifo_0 16 16
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p_sys_wfifo [current_bd_instance .] sys_wfifo_1 16 16
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p_sys_wfifo [current_bd_instance .] sys_wfifo_2 16 16
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p_sys_wfifo [current_bd_instance .] sys_wfifo_3 16 16
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ad_connect axi_ad9361_clk sys_wfifo_0/adc_clk
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ad_connect axi_ad9361_clk sys_wfifo_1/adc_clk
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ad_connect axi_ad9361_clk sys_wfifo_2/adc_clk
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ad_connect axi_ad9361_clk sys_wfifo_3/adc_clk
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ad_connect sys_wfifo_0/adc_wr axi_ad9361/adc_valid_i0
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ad_connect sys_wfifo_1/adc_wr axi_ad9361/adc_valid_q0
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ad_connect sys_wfifo_2/adc_wr axi_ad9361/adc_valid_i1
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ad_connect sys_wfifo_3/adc_wr axi_ad9361/adc_valid_q1
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ad_connect sys_wfifo_0/adc_wdata axi_ad9361/adc_data_i0
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ad_connect sys_wfifo_1/adc_wdata axi_ad9361/adc_data_q0
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ad_connect sys_wfifo_2/adc_wdata axi_ad9361/adc_data_i1
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ad_connect sys_wfifo_3/adc_wdata axi_ad9361/adc_data_q1
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ad_connect sys_cpu_clk ila_adc/clk
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ad_connect sys_cpu_clk sys_wfifo_0/dma_clk
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ad_connect sys_cpu_clk sys_wfifo_1/dma_clk
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ad_connect sys_cpu_clk sys_wfifo_2/dma_clk
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ad_connect sys_cpu_clk sys_wfifo_3/dma_clk
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ad_connect sys_wfifo_0/dma_wr ila_adc/probe0
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ad_connect sys_wfifo_1/dma_wr ila_adc/probe1
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ad_connect sys_wfifo_2/dma_wr ila_adc/probe2
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ad_connect sys_wfifo_3/dma_wr ila_adc/probe3
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ad_connect sys_wfifo_0/dma_wdata ila_adc/probe4
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ad_connect sys_wfifo_1/dma_wdata ila_adc/probe5
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ad_connect sys_wfifo_2/dma_wdata ila_adc/probe6
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ad_connect sys_wfifo_3/dma_wdata ila_adc/probe7
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