2019-12-05 08:59:26 +00:00
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# Primary clock definitions
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create_clock -name refclk -period 1.29 [get_ports fpga_refclk_in_p]
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# device clock
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create_clock -name tx_device_clk -period 2.58 [get_ports clkin6_p]
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create_clock -name rx_device_clk -period 2.58 [get_ports clkin10_p]
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# Constraint SYSREFs
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# Assumption is that REFCLK and SYSREF have similar propagation delay,
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# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
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set_input_delay -clock [get_clocks tx_device_clk] \
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[get_property PERIOD [get_clocks tx_device_clk]] \
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[get_ports {sysref2_*}]
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2020-12-17 13:44:30 +00:00
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# For transceiver output clocks use reference clock divided by two
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# This will help autoderive the clocks correcly
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
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set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
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set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
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