2017-01-31 14:43:40 +00:00
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source ../../common/zed/zed_system_bd.tcl
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source ../common/m2k_bd.tcl
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2017-04-19 13:47:21 +00:00
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# Use the 100 MHz clock for video DMA, the AXI interface clock is to slow for
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# this in this project.
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set video_dma_clocks [list \
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axi_hp0_interconnect/ACLK \
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axi_hp0_interconnect/M00_ACLK \
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axi_hp0_interconnect/S00_ACLK \
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sys_ps7/S_AXI_HP0_ACLK \
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axi_hdmi_dma/m_axi_mm2s_aclk \
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axi_hdmi_dma/m_axis_mm2s_aclk \
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axi_hdmi_core/vdma_clk
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]
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set video_dma_resets [list \
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axi_hp0_interconnect/ARESETN \
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axi_hp0_interconnect/M00_ARESETN \
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axi_hp0_interconnect/S00_ARESETN \
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]
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 100.0
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ad_ip_instance proc_sys_reset video_dma_reset
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ad_connect sys_ps7/FCLK_CLK1 video_dma_reset/slowest_sync_clk
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ad_connect sys_rstgen/peripheral_aresetn video_dma_reset/ext_reset_in
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foreach clk $video_dma_clocks {
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ad_disconnect /sys_cpu_clk $clk
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ad_connect $clk sys_ps7/FCLK_CLK1
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}
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foreach rst $video_dma_resets {
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ad_disconnect /sys_cpu_resetn $rst
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ad_connect $rst video_dma_reset/peripheral_aresetn
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}
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