pluto_hdl_adi/library/axi_ad9265/axi_ad9265_ip.tcl

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###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
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# ip
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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adi_ip_create axi_ad9265
adi_ip_files axi_ad9265 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \
"$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \
"$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \
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"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
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"axi_ad9265_pnmon.v" \
"axi_ad9265_if.v" \
"axi_ad9265_channel.v" \
"axi_ad9265.v" ]
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adi_ip_properties axi_ad9265
adi_init_bd_tcl
adi_ip_bd axi_ad9265 "bd/bd.tcl"
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set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9265} [ipx::current_core]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk_in_P xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
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ipx::save_core [ipx::current_core]