pluto_hdl_adi/library/altera/common/ad_serdes_clk.v

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// serial data output interface: serdes(x8)

`timescale 1ps/1ps

module ad_serdes_clk (

  // clock and divided clock

  mmcm_rst,
  clk_in_p,
  clk_in_n,

  clk,
  div_clk,
  out_clk,
  loaden,
  phase,

  // drp interface

  up_clk,
  up_rstn,
  up_drp_sel,
  up_drp_wr,
  up_drp_addr,
  up_drp_wdata,
  up_drp_rdata,
  up_drp_ready,
  up_drp_locked);

  // parameters

  parameter       MODE = "TX";

  // clock and divided clock

  input           mmcm_rst;
  input           clk_in_p;
  input           clk_in_n;

  output          clk;
  output          div_clk;
  output          out_clk;
  output          loaden;
  output  [ 7:0]  phase;

  // drp interface

  input           up_clk;
  input           up_rstn;
  input           up_drp_sel;
  input           up_drp_wr;
  input   [11:0]  up_drp_addr;
  input   [15:0]  up_drp_wdata;
  output  [15:0]  up_drp_rdata;
  output          up_drp_ready;
  output          up_drp_locked;

  wire            locked;

  // ground the unused outputs

  assign up_drp_rdata = 15'b0;
  assign up_drp_ready = 1'b0;
  assign up_drp_locked = locked;

  generate if (MODE == "TX") begin

    assign phase = 8'h0;

    alt_clk i_alt_clk (
      .locked (locked),         // locked.export
      .outclk_0 (clk),          // outclk0.clk
      .outclk_1 (loaden),       // outclk1.clk
      .outclk_2 (div_clk),      // outclk2.clk
      .outclk_3 (out_clk),      // outclk3.clk
      .reconfig_from_pll (),    // reconfig_from_pll.reconfig_from_pll
      .reconfig_to_pll (),      // reconfig_to_pll.reconfig_to_pll
      .refclk (clk_in_p),       // refclk.clk
      .rst (mmcm_rst)           // reset.reset
    );

    // TODO: Add Altera PLL Reconfig IP

  end else begin

  alt_clk i_alt_clk (
    .locked (locked),         // locked.export
    .outclk_0 (clk),          // outclk0.clk
    .outclk_1 (loaden),       // outclk1.clk
    .outclk_2 (div_clk),      // outclk2.clk
    .outclk_3 (out_clk),      // outclk3.clk
    .reconfig_from_pll (),    // reconfig_from_pll.reconfig_from_pll
    .reconfig_to_pll (),      // reconfig_to_pll.reconfig_to_pll
    .phout (phase),
    .refclk (clk_in_p),       // refclk.clk
    .rst (mmcm_rst)           // reset.reset
  );

  end
  endgenerate

endmodule