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axi_ad7616: Initial commit
2015-11-10 11:32:56 +00:00
// ***************************************************************************
// ***************************************************************************
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
license: Add some clarification to the header license
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// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
license: Fix a spelling mistake
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// freedoms and responsibilities that he or she has by using this source/core.
license: Add some clarification to the header license
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//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
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//
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
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// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
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//
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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// 1. The GNU General Public License version 2 as published by the
license: Add some clarification to the header license
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// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
// OR
//
license: Add some clarification to the header license
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// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
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//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
all: Update verilog files to verilog-2001
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module axi_ad7616 #(
parameter ID = 0,
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
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parameter IF_TYPE = 1
) (
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// physical data interface
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output rx_sclk,
output rx_cs_n,
output rx_sdo,
ad7616_sdz: Fix the project, after SDI ports were merged Update the project to support the SDI port merge patch: 4d54c7e
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input [ 1:0] rx_sdi,
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output [15:0] rx_db_o,
input [15:0] rx_db_i,
output rx_db_t,
output rx_rd_n,
output rx_wr_n,
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// physical control interface
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output rx_cnvst,
input rx_busy,
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// AXI Slave Memory Map
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input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size The external s_axi_{awaddr,araddr} signals that are connect to the core have their width set according to the specified size of the register map. If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently is for many cores) the MSBs of those signals are left unconnected, which generates a warning. To avoid this make sure that the signal width matches the declared register map size. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size The external s_axi_{awaddr,araddr} signals that are connect to the core have their width set according to the specified size of the register map. If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently is for many cores) the MSBs of those signals are left unconnected, which generates a warning. To avoid this make sure that the signal width matches the declared register map size. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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input [15:0] s_axi_araddr,
all: Update verilog files to verilog-2001
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input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
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// Write FIFO interface
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all: Update verilog files to verilog-2001
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output adc_valid,
output [15:0] adc_data,
output adc_sync,
axi_ad7616: Initial commit
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libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
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output irq
);
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
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localparam NUM_OF_SDI = 2;
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localparam SERIAL = 0;
localparam PARALLEL = 1;
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localparam NEG_EDGE = 1;
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// internal registers
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reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
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// internal signals
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wire up_clk;
wire up_rstn;
wire up_rst;
wire up_rreq_s;
up_axi_update: ADDRESS_WIDTH parameter is now a localparam ADDRESS_WIDTH is now AXI_ADDRESS_WIDTH - 2; up_axi instantiations will set AXI_ADDRESS_WIDTH instead of ADDRESS_WIDTH;
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wire [13:0] up_raddr_s;
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wire up_wreq_s;
up_axi_update: ADDRESS_WIDTH parameter is now a localparam ADDRESS_WIDTH is now AXI_ADDRESS_WIDTH - 2; up_axi instantiations will set AXI_ADDRESS_WIDTH instead of ADDRESS_WIDTH;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
wire up_wack_if_s;
wire up_rack_if_s;
wire [31:0] up_rdata_if_s;
wire up_wack_cntrl_s;
wire up_rack_cntrl_s;
wire [31:0] up_rdata_cntrl_s;
wire trigger_s;
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wire rd_req_s;
wire wr_req_s;
wire [15:0] wr_data_s;
wire [15:0] rd_data_s;
axi_ad7616: Fix the rd_db_valid generation and do some cosmetic changes.
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wire rd_valid_s;
axi_ad7616: Add burst counter to the parallel interface With this counter the parallel logic supports the burst sequencer.
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wire [ 4:0] burst_length_s;
axi_ad7616: Add M_AXIS_READY_ENABLE parameter m_axis_ready can be driven by the DMA or can have a constant active state. By default is always one.
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wire m_axis_ready_s;
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wire m_axis_valid_s;
wire [15:0] m_axis_data_s;
wire m_axis_xfer_req_s;
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// defaults
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
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assign up_rst = ~s_axi_aresetn;
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// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_wack <= up_wack_if_s | up_wack_cntrl_s;
up_rack <= up_rack_if_s | up_rack_cntrl_s;
up_rdata <= up_rdata_if_s | up_rdata_cntrl_s;
end
end
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generate if (IF_TYPE == SERIAL) begin
// ground all parallel interface signals
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assign rx_db_o = 16'b0;
assign rx_rd_n = 1'b0;
assign rx_wr_n = 1'b0;
axi_ad7616: Add the control module to the core, finish up SPI integration
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axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
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// SPI Framework instances and logic
wire spi_resetn_s;
wire s0_cmd_ready_s;
wire s0_cmd_valid_s;
wire [15:0] s0_cmd_data_s;
wire s0_sdo_data_ready_s;
wire s0_sdo_data_valid_s;
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wire [ 7:0] s0_sdo_data_s;
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
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wire s0_sdi_data_ready_s;
wire s0_sdi_data_valid_s;
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wire [15:0] s0_sdi_data_s;
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wire s0_sync_ready_s;
wire s0_sync_valid_s;
wire [ 7:0] s0_sync_s;
wire s1_cmd_ready_s;
wire s1_cmd_valid_s;
wire [15:0] s1_cmd_data_s;
wire s1_sdo_data_ready_s;
wire s1_sdo_data_valid_s;
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wire [ 7:0] s1_sdo_data_s;
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wire s1_sdi_data_ready_s;
wire s1_sdi_data_valid_s;
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wire [15:0] s1_sdi_data_s;
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
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wire s1_sync_ready_s;
wire s1_sync_valid_s;
wire [ 7:0] s1_sync_s;
wire m_cmd_ready_s;
wire m_cmd_valid_s;
wire [15:0] m_cmd_data_s;
wire m_sdo_data_ready_s;
wire m_sdo_data_valid_s;
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wire [7:0] m_sdo_data_s;
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wire m_sdi_data_ready_s;
wire m_sdi_data_valid_s;
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wire [15:0] m_sdi_data_s;
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wire m_sync_ready_s;
wire m_sync_valid_s;
wire [ 7:0] m_sync_s;
wire offload0_cmd_wr_en_s;
wire [15:0] offload0_cmd_wr_data_s;
wire offload0_sdo_wr_en_s;
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wire [ 7:0] offload0_sdo_wr_data_s;
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
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wire offload0_mem_reset_s;
wire offload0_enable_s;
wire offload0_enabled_s;
axi_ad7616: Fix sync port
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wire offload_sync_ready_s;
wire offload_sync_valid_s;
wire [ 7:0] offload_sync_data_s;
axi_ad7616: Add spi engine to the core
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axi_spi_engine #(
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.DATA_WIDTH (8),
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.NUM_OF_SDI (NUM_OF_SDI),
.NUM_OFFLOAD(1),
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.MM_IF_TYPE(1)
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) i_axi_spi_engine (
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.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_if_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_if_s),
.up_rack (up_rack_if_s),
axi_ad7616: Add the control module to the core, finish up SPI integration
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.irq (irq),
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.spi_clk (up_clk),
.spi_resetn (spi_resetn_s),
axi_ad7616: Add the control module to the core, finish up SPI integration
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.cmd_ready (s0_cmd_ready_s),
.cmd_valid (s0_cmd_valid_s),
.cmd_data (s0_cmd_data_s),
.sdo_data_ready (s0_sdo_data_ready_s),
.sdo_data_valid (s0_sdo_data_valid_s),
.sdo_data (s0_sdo_data_s),
.sdi_data_ready (s0_sdi_data_ready_s),
.sdi_data_valid (s0_sdi_data_valid_s),
.sdi_data (s0_sdi_data_s),
.sync_ready (s0_sync_ready_s),
.sync_valid (s0_sync_valid_s),
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
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.sync_data (s0_sync_s),
axi_ad7616: Fix sync port
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.offload_sync_ready (offload_sync_ready_s),
.offload_sync_valid (offload_sync_valid_s),
.offload_sync_data (offload_sync_data_s),
axi_ad7616: Add the control module to the core, finish up SPI integration
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.offload0_cmd_wr_en (offload0_cmd_wr_en_s),
.offload0_cmd_wr_data (offload0_cmd_wr_data_s),
.offload0_sdo_wr_en (offload0_sdo_wr_en_s),
.offload0_sdo_wr_data (offload0_sdo_wr_data_s),
.offload0_mem_reset (offload0_mem_reset_s),
.offload0_enable (offload0_enable_s),
.offload0_enabled(offload0_enabled_s));
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spi_engine_offload #(
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.DATA_WIDTH (8),
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.NUM_OF_SDI (NUM_OF_SDI)
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) i_spi_engine_offload (
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.ctrl_clk (up_clk),
.ctrl_cmd_wr_en (offload0_cmd_wr_en_s),
.ctrl_cmd_wr_data (offload0_cmd_wr_data_s),
.ctrl_sdo_wr_en (offload0_sdo_wr_en_s),
.ctrl_sdo_wr_data (offload0_sdo_wr_data_s),
.ctrl_enable (offload0_enable_s),
.ctrl_enabled (offload0_enabled_s),
.ctrl_mem_reset (offload0_mem_reset_s),
axi_ad7616: Add spi engine to the core
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.spi_clk (up_clk),
.spi_resetn (spi_resetn_s),
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
.trigger (trigger_s),
.cmd_valid (s1_cmd_valid_s),
.cmd_ready (s1_cmd_ready_s),
.cmd (s1_cmd_data_s),
.sdo_data_valid (s1_sdo_data_valid_s),
.sdo_data_ready (s1_sdo_data_ready_s),
.sdo_data (s1_sdo_data_s),
.sdi_data_valid (s1_sdi_data_valid_s),
.sdi_data_ready (s1_sdi_data_ready_s),
.sdi_data (s1_sdi_data_s),
.sync_valid (s1_sync_valid_s),
.sync_ready (s1_sync_ready_s),
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
2015-12-14 14:00:56 +00:00
.sync_data (s1_sync_s),
axi_ad7616: Fix sync port
2021-11-16 11:40:46 +00:00
.status_sync_ready (offload_sync_ready_s),
.status_sync_valid (offload_sync_valid_s),
.status_sync_data (offload_sync_data_s),
axi_ad7616: Change the DMA interface type to Write FIFO
2016-06-29 11:11:02 +00:00
.offload_sdi_valid (m_axis_valid_s),
axi_ad7616: Add M_AXIS_READY_ENABLE parameter m_axis_ready can be driven by the DMA or can have a constant active state. By default is always one.
2016-03-15 16:38:55 +00:00
.offload_sdi_ready (m_axis_ready_s),
axi_ad7616: Change the DMA interface type to Write FIFO
2016-06-29 11:11:02 +00:00
.offload_sdi_data (m_axis_data_s));
axi_ad7616: Add spi engine to the core
2015-11-12 14:12:16 +00:00
spi_engine_interconnect #(
axi_ad7616: Change the DMA interface type to Write FIFO
2016-06-29 11:11:02 +00:00
.DATA_WIDTH (8),
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
2015-12-14 14:00:56 +00:00
.NUM_OF_SDI (NUM_OF_SDI)
axi_ad7616: Add spi engine to the core
2015-11-12 14:12:16 +00:00
) i_spi_engine_interconnect (
.clk (up_clk),
.resetn (spi_resetn_s),
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
.m_cmd_valid (m_cmd_valid_s),
.m_cmd_ready (m_cmd_ready_s),
.m_cmd_data (m_cmd_data_s),
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
2015-12-14 14:00:56 +00:00
.m_sdo_valid (m_sdo_data_valid_s),
.m_sdo_ready (m_sdo_data_ready_s),
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
.m_sdo_data (m_sdo_data_s),
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
2015-12-14 14:00:56 +00:00
.m_sdi_valid (m_sdi_data_valid_s),
.m_sdi_ready (m_sdi_data_ready_s),
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
.m_sdi_data (m_sdi_data_s),
.m_sync_valid (m_sync_valid_s),
.m_sync_ready (m_sync_ready_s),
.m_sync (m_sync_s),
.s0_cmd_valid (s0_cmd_valid_s),
.s0_cmd_ready (s0_cmd_ready_s),
.s0_cmd_data (s0_cmd_data_s),
.s0_sdo_valid (s0_sdo_data_valid_s),
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
2015-12-14 14:00:56 +00:00
.s0_sdo_ready (s0_sdo_data_ready_s),
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
.s0_sdo_data (s0_sdo_data_s),
.s0_sdi_valid (s0_sdi_data_valid_s),
.s0_sdi_ready (s0_sdi_data_ready_s),
.s0_sdi_data (s0_sdi_data_s),
.s0_sync_valid (s0_sync_valid_s),
.s0_sync_ready (s0_sync_ready_s),
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
2015-12-14 14:00:56 +00:00
.s0_sync (s0_sync_s),
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
.s1_cmd_valid (s1_cmd_valid_s),
.s1_cmd_ready (s1_cmd_ready_s),
.s1_cmd_data (s1_cmd_data_s),
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
2015-12-14 14:00:56 +00:00
.s1_sdo_valid (s1_sdo_data_valid_s),
.s1_sdo_ready (s1_sdo_data_ready_s),
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
.s1_sdo_data (s1_sdo_data_s),
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
2015-12-14 14:00:56 +00:00
.s1_sdi_valid (s1_sdi_data_valid_s),
.s1_sdi_ready (s1_sdi_data_ready_s),
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
.s1_sdi_data (s1_sdi_data_s),
.s1_sync_valid (s1_sync_valid_s),
.s1_sync_ready (s1_sync_ready_s),
.s1_sync (s1_sync_s));
axi_ad7616: Add spi engine to the core
2015-11-12 14:12:16 +00:00
spi_engine_execution #(
axi_ad7616: Change the DMA interface type to Write FIFO
2016-06-29 11:11:02 +00:00
.DATA_WIDTH (8),
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
2015-12-14 14:00:56 +00:00
.NUM_OF_SDI (NUM_OF_SDI)
axi_ad7616: Add spi engine to the core
2015-11-12 14:12:16 +00:00
) i_spi_engine_execution (
.clk (up_clk),
.resetn (spi_resetn_s),
.active (),
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
.cmd_ready (m_cmd_ready_s),
.cmd_valid (m_cmd_valid_s),
.cmd (m_cmd_data_s),
.sdo_data_valid (m_sdo_data_valid_s),
.sdo_data_ready (m_sdo_data_ready_s),
.sdo_data (m_sdo_data_s),
.sdi_data_ready (m_sdi_data_ready_s),
.sdi_data_valid (m_sdi_data_valid_s),
.sdi_data (m_sdi_data_s),
.sync_ready (m_sync_ready_s),
.sync_valid (m_sync_valid_s),
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
2015-12-14 14:00:56 +00:00
.sync (m_sync_s),
axi_ad7616: Rename the physical interface signals to rx_* No functional modification.
2016-07-01 08:12:00 +00:00
.sclk (rx_sclk),
.sdo (rx_sdo),
axi_ad7616: Add spi engine to the core
2015-11-12 14:12:16 +00:00
.sdo_t (),
ad7616_sdz: Fix the project, after SDI ports were merged Update the project to support the SDI port merge patch: 4d54c7e
2020-05-19 10:55:49 +00:00
.sdi (rx_sdi),
axi_ad7616: Rename the physical interface signals to rx_* No functional modification.
2016-07-01 08:12:00 +00:00
.cs (rx_cs_n),
axi_ad7616: Add spi engine to the core
2015-11-12 14:12:16 +00:00
.three_wire ());
axi_ad7616: Change the DMA interface type to Write FIFO
2016-06-29 11:11:02 +00:00
axi_ad7616_maxis2wrfifo #(
.DATA_WIDTH(16)
) i_maxis2wrfifo (
.clk(up_clk),
.rstn(up_rstn),
.sync_in(trigger_s),
.m_axis_data(m_axis_data_s),
.m_axis_ready(m_axis_ready_s),
.m_axis_valid(m_axis_valid_s),
.fifo_wr_en(adc_valid),
axi_ad7616: Rename the physical interface signals to rx_* No functional modification.
2016-07-01 08:12:00 +00:00
.fifo_wr_data(adc_data),
axi_ad7616: Add missing port to instantiation
2018-02-27 14:14:35 +00:00
.fifo_wr_sync(adc_sync),
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-04-08 10:21:52 +00:00
.fifo_wr_xfer_req(1'b1));
axi_ad7616: Add support for parallel interface
2016-01-28 10:37:22 +00:00
axi_ad7616: Change the DMA interface type to Write FIFO
2016-06-29 11:11:02 +00:00
end
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
2015-12-14 14:00:56 +00:00
endgenerate
axi_ad7616: Add spi engine to the core
2015-11-12 14:12:16 +00:00
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
generate if (IF_TYPE == PARALLEL) begin
axi_ad7616: Add support for parallel interface
2016-01-28 10:37:22 +00:00
axi_ad7616: Rename the physical interface signals to rx_* No functional modification.
2016-07-01 08:12:00 +00:00
assign rx_sclk = 1'h0;
assign rx_sdo = 1'h0;
axi_ad7616: Add support for parallel interface
2016-01-28 10:37:22 +00:00
assign irq = 1'h0;
assign up_wack_if_s = 1'h0;
assign up_rack_if_s = 1'h0;
assign up_rdata_if_s = 1'h0;
axi_ad7616_pif i_ad7616_parallel_interface (
axi_ad7616: Rename the physical interface signals to rx_* No functional modification.
2016-07-01 08:12:00 +00:00
.cs_n (rx_cs_n),
.db_o (rx_db_o),
.db_i (rx_db_i),
.db_t (rx_db_t),
.rd_n (rx_rd_n),
.wr_n (rx_wr_n),
.adc_data (adc_data),
axi_ad7616: Change the DMA interface type to Write FIFO
2016-06-29 11:11:02 +00:00
.adc_valid (adc_valid),
.adc_sync (adc_sync),
.end_of_conv (trigger_s),
axi_ad7616: Add burst counter to the parallel interface With this counter the parallel logic supports the burst sequencer.
2016-06-29 11:17:28 +00:00
.burst_length(burst_length_s),
axi_ad7616: Change the DMA interface type to Write FIFO
2016-06-29 11:11:02 +00:00
.clk (up_clk),
.rstn (up_rstn),
.rd_req (rd_req_s),
.wr_req (wr_req_s),
.wr_data (wr_data_s),
.rd_data (rd_data_s),
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-04-08 10:21:52 +00:00
.rd_valid (rd_valid_s));
axi_ad7616: Add support for parallel interface
2016-01-28 10:37:22 +00:00
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
end
endgenerate
axi_ad7616_control #(
axi_ad7616: Add support for parallel interface
2016-01-28 10:37:22 +00:00
.ID(ID),
.IF_TYPE(IF_TYPE)
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
) i_ad7616_control (
axi_ad7616: Rename the physical interface signals to rx_* No functional modification.
2016-07-01 08:12:00 +00:00
.cnvst (rx_cnvst),
.busy (rx_busy),
axi_ad7616: Add burst counter to the parallel interface With this counter the parallel logic supports the burst sequencer.
2016-06-29 11:17:28 +00:00
.up_burst_length (burst_length_s),
axi_ad7616: Add support for parallel interface
2016-01-28 10:37:22 +00:00
.up_read_data (rd_data_s),
axi_ad7616: Fix the rd_db_valid generation and do some cosmetic changes.
2016-04-25 08:28:22 +00:00
.up_read_valid (rd_valid_s),
axi_ad7616: Add support for parallel interface
2016-01-28 10:37:22 +00:00
.up_write_data (wr_data_s),
.up_read_req (rd_req_s),
.up_write_req (wr_req_s),
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
.end_of_conv (trigger_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
2015-12-14 14:00:56 +00:00
.up_wdata (up_wdata_s),
.up_wack (up_wack_cntrl_s),
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
2015-12-14 14:00:56 +00:00
.up_rdata (up_rdata_cntrl_s),
.up_rack (up_rack_cntrl_s));
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 16:14:21 +00:00
axi_ad7616: Initial commit
2015-11-10 11:32:56 +00:00
// up bus interface
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
2015-12-14 14:00:56 +00:00
up_axi #(
up_axi_update: ADDRESS_WIDTH parameter is now a localparam ADDRESS_WIDTH is now AXI_ADDRESS_WIDTH - 2; up_axi instantiations will set AXI_ADDRESS_WIDTH instead of ADDRESS_WIDTH;
2019-07-15 15:16:07 +00:00
.AXI_ADDRESS_WIDTH (16)
axi_ad7616: Update core + Both the data width and number of SDI lines are configurable + SER1W line is hardware configurable, it was removed from the IP + Add 'Hardware mode' support for the controller
2015-12-14 14:00:56 +00:00
) i_up_axi (
axi_ad7616: Initial commit
2015-11-10 11:32:56 +00:00
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule