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pluto_hdl_adi/library/data_offload/Makefile

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data_offload: Initial commit
2021-03-15 08:50:39 +00:00
####################################################################################
Makefiles: Update header with the appropriate license
2021-09-15 15:03:11 +00:00
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
data_offload: Initial commit
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## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := data_offload
GENERIC_DEPS += ../common/ad_axis_inf_rx.v
Makefile: Fix misc makefiles from projects and library
2021-09-30 13:20:02 +00:00
GENERIC_DEPS += ../common/ad_mem_asym.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += data_offload.v
data_offload: Initial commit
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GENERIC_DEPS += data_offload_fsm.v
GENERIC_DEPS += data_offload_regmap.v
XILINX_DEPS += data_offload_ip.tcl
Makefile: Fix misc makefiles from projects and library
2021-09-30 13:20:02 +00:00
XILINX_DEPS += data_offload_sv.ttcl
data_offload: Initial commit
2021-03-15 08:50:39 +00:00
data_offload: Refactor core Deprecate unused parameters. Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for now. However in the future we might want to add support for non pow2 sizes so register map is not changed. Change transfer length to -1 value to spare logic. Change FIFO interface to AXIS to have backpressure, this allows the implementation of data movement logic in the storage unit and let the FSM handle high level control an synchronization and control the storage unit through a control interface. Refactor FSM to have preparation states where slow storages can be configured and started ahead of the data handling. Make bypasss FIFO optional since in some cases causes timing failures due the missing output register of the memory. This can be targeted in a later commit. Hook up underflow/overflow to regmap useful in case of external memory where rate drops due misconfiguration can be detected. Cleanup for verilator. Scripting: Add HBM and DDR external memory support using util_hbm IP Replace asym_block_ram with util_do_ram IP
2022-02-24 11:44:05 +00:00
XILINX_DEPS += ../interfaces/if_do_ctrl.xml
XILINX_DEPS += ../interfaces/if_do_ctrl_rtl.xml
data_offload: Initial commit
2021-03-15 08:50:39 +00:00
XILINX_LIB_DEPS += util_axis_fifo_asym
XILINX_LIB_DEPS += util_cdc
data_offload: Refactor core Deprecate unused parameters. Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for now. However in the future we might want to add support for non pow2 sizes so register map is not changed. Change transfer length to -1 value to spare logic. Change FIFO interface to AXIS to have backpressure, this allows the implementation of data movement logic in the storage unit and let the FSM handle high level control an synchronization and control the storage unit through a control interface. Refactor FSM to have preparation states where slow storages can be configured and started ahead of the data handling. Make bypasss FIFO optional since in some cases causes timing failures due the missing output register of the memory. This can be targeted in a later commit. Hook up underflow/overflow to regmap useful in case of external memory where rate drops due misconfiguration can be detected. Cleanup for verilator. Scripting: Add HBM and DDR external memory support using util_hbm IP Replace asym_block_ram with util_do_ram IP
2022-02-24 11:44:05 +00:00
XILINX_INTERFACE_DEPS += interfaces
data_offload: Initial commit
2021-03-15 08:50:39 +00:00
include ../scripts/library.mk