70 lines
1.7 KiB
VHDL
70 lines
1.7 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity dma_fifo is
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generic (
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RAM_ADDR_WIDTH : integer := 3;
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FIFO_DWIDTH : integer := 32
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);
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port (
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clk : in std_logic;
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resetn : in std_logic;
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fifo_reset : in std_logic;
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-- Write port
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in_stb : in std_logic;
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in_ack : out std_logic;
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in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
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-- Read port
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out_stb : out std_logic;
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out_ack : in std_logic;
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out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0)
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);
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end;
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architecture imp of dma_fifo is
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constant FIFO_MAX : natural := 2**RAM_ADDR_WIDTH -1;
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type MEM is array (0 to FIFO_MAX) of std_logic_vector(FIFO_DWIDTH - 1 downto 0);
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signal data_fifo : MEM;
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signal wr_addr : natural range 0 to FIFO_MAX;
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signal rd_addr : natural range 0 to FIFO_MAX;
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signal full, empty : Boolean;
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begin
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in_ack <= '0' when full else '1';
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out_stb <= '0' when empty else '1';
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out_data <= data_fifo(rd_addr);
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fifo: process (clk) is
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variable free_cnt : integer range 0 to FIFO_MAX + 1;
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begin
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if rising_edge(clk) then
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if (resetn = '0') or (fifo_reset = '1') then
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wr_addr <= 0;
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rd_addr <= 0;
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free_cnt := FIFO_MAX + 1;
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empty <= True;
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full <= False;
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else
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if in_stb = '1' and not full then
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data_fifo(wr_addr) <= in_data;
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wr_addr <= (wr_addr + 1) mod (FIFO_MAX + 1);
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free_cnt := free_cnt - 1;
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end if;
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if out_ack = '1' and not empty then
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rd_addr <= (rd_addr + 1) mod (FIFO_MAX + 1);
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free_cnt := free_cnt + 1;
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end if;
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full <= free_cnt = 0;
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empty <= free_cnt = FIFO_MAX + 1;
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end if;
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end if;
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end process;
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end;
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