zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/library/util_dacfifo/util_dacfifo_constr.sdc

20 lines
1023 B
Plaintext
Raw Normal View History

Add copyright and license to .sdc files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-10 08:36:06 +00:00
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
adc/dac-fifo altera cores
2017-02-28 18:30:50 +00:00
util_dacfifo/constraints- false paths for bypass
2017-03-06 15:33:07 +00:00
set_false_path -to [get_registers *dac_bypass_m1*]
set_false_path -to [get_registers *dma_bypass_m1*]
util_dacfifo: Update the util_dacfifo Fix bypass and undate the general functionality. If bypass enabled the FIFO will function as a normal CDC FIFO.
2017-03-03 16:43:36 +00:00
set_false_path -from [get_registers *dac_raddr_g*] -to [get_registers *dma_raddr_m1*]
set_false_path -from [get_registers *dma_waddr_g*] -to [get_registers *dac_waddr_m1*]
set_false_path -from [get_registers *dma_lastaddr_g*] -to [get_registers *dac_lastaddr_m1*]
set_false_path -from [get_registers *dma_xfer_out_fifo*] -to [get_registers *dac_xfer_out_fifo_m1*]
util_dacfifo: Update the bypass logic
2018-08-21 12:59:25 +00:00
set_false_path -from [get_registers *dma_mem_waddr_g*] -to [get_registers *dac_mem_waddr_m1*]
set_false_path -from [get_registers *dac_mem_raddr_g*] -to [get_registers *dma_mem_raddr_m1*]
set_false_path -to [get_registers *dma_rst_m1*]
util_dacfifo: Fix the reset logic of the module Both the DMA and DAC side should be in reset at the positive edge of the dma_xfer_req, so we can re-initialize the buffer.
2018-08-22 12:05:00 +00:00
set_false_path -to [get_registers *dac_xfer_req_m1*]
util_dacfifo: Update the bypass logic
2018-08-21 12:59:25 +00:00