2023-07-06 12:08:22 +00:00
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###############################################################################
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## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2020-03-15 22:40:48 +00:00
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2021-02-25 09:41:57 +00:00
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package require qsys 14.0
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2022-07-12 11:06:15 +00:00
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source ../../scripts/adi_env.tcl
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2020-03-15 22:40:48 +00:00
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source ../scripts/adi_ip_intel.tcl
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set_module_property NAME sysid_rom
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set_module_property DESCRIPTION "System ID ROM"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME sysid_rom
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# source files
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ad_ip_files sysid_rom [list \
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"sysid_rom.v"]
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# IP parameters
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add_parameter ROM_WIDTH INTEGER 32
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set_parameter_property ROM_WIDTH DEFAULT_VALUE 32
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set_parameter_property ROM_WIDTH DISPLAY_NAME "ROM width"
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set_parameter_property ROM_WIDTH UNITS None
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set_parameter_property ROM_WIDTH HDL_PARAMETER true
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add_parameter ROM_ADDR_BITS INTEGER 6
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set_parameter_property ROM_ADDR_BITS DEFAULT_VALUE 6
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set_parameter_property ROM_ADDR_BITS DISPLAY_NAME "ROM address bits"
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set_parameter_property ROM_ADDR_BITS HDL_PARAMETER true
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add_parameter PATH_TO_FILE STRING "path_to_mem_init_file"
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set_parameter_property PATH_TO_FILE DISPLAY_NAME "Path to file"
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set_parameter_property PATH_TO_FILE HDL_PARAMETER true
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# external clock and control/status ports
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ad_interface clock clk input 1
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ad_interface signal rom_data output ROM_WIDTH rom_data
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ad_interface signal rom_addr input ROM_ADDR_BITS
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