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pluto_hdl_adi/projects/adv7511/vc707/system_bd.tcl

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Initial check in of VC707 base project - All source files for the VC707 base project - Update the common base system to the new naming convention
2014-03-10 15:26:17 +00:00
source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
VC707 basesys: General fixes, actual status: working - Add an auxiliary cpu interconnect - Add an auxiliary interrupt concatenation module - Add new MIG file, current frequency of the DDR interface is 100 Mhz - Memory interconnect optimisation strategy is 'Maximize Performance'
2014-03-24 11:07:48 +00:00
set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
Initial check in of VC707 base project - All source files for the VC707 base project - Update the common base system to the new naming convention
2014-03-10 15:26:17 +00:00
set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect
set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect
VC707 basesys: General fixes, actual status: working - Add an auxiliary cpu interconnect - Add an auxiliary interrupt concatenation module - Add new MIG file, current frequency of the DDR interface is 100 Mhz - Memory interconnect optimisation strategy is 'Maximize Performance'
2014-03-24 11:07:48 +00:00
set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc
Initial check in of VC707 base project - All source files for the VC707 base project - Update the common base system to the new naming convention
2014-03-10 15:26:17 +00:00