2018-03-23 11:55:11 +00:00
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####################################################################################
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2023-02-07 11:30:08 +00:00
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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2021-09-13 20:50:01 +00:00
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## SPDX short identifier: BSD-1-Clause
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2018-03-23 11:55:11 +00:00
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####################################################################################
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# Assumes this file is in library/scripts/library.mk
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HDL_LIBRARY_PATH := $(subst scripts/library.mk,,$(lastword $(MAKEFILE_LIST)))
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2018-03-25 07:21:37 +00:00
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include $(HDL_LIBRARY_PATH)../quiet.mk
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2019-03-14 13:50:21 +00:00
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CASE_INCLUDE := $(wildcard temporary_case_dependencies.mk)
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ifneq ($(CASE_INCLUDE),)
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include temporary_case_dependencies.mk
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endif
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2018-03-23 11:55:11 +00:00
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VIVADO := vivado -mode batch -source
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2019-03-14 13:50:21 +00:00
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CLEAN_TARGET += *.cache
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2018-03-23 11:55:11 +00:00
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CLEAN_TARGET += *.data
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CLEAN_TARGET += *.xpr
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CLEAN_TARGET += *.log
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CLEAN_TARGET += component.xml
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CLEAN_TARGET += *.jou
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CLEAN_TARGET += xgui
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2023-02-07 11:30:08 +00:00
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CLEAN_TARGET += gui
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CLEAN_TARGET += *.runs
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CLEAN_TARGET += *.gen
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2018-03-23 11:55:11 +00:00
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CLEAN_TARGET += *.ip_user_files
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CLEAN_TARGET += *.srcs
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CLEAN_TARGET += *.hw
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CLEAN_TARGET += *.sim
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CLEAN_TARGET += .Xil
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2018-08-13 13:59:02 +00:00
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CLEAN_TARGET += .timestamp_intel
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2021-02-09 10:29:26 +00:00
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CLEAN_TARGET += *.hbs
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2022-09-23 12:07:45 +00:00
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CLEAN_TARGET += tb/*.log
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CLEAN_TARGET += tb/*.xml
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CLEAN_TARGET += tb/*.jou
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CLEAN_TARGET += tb/*.dir
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CLEAN_TARGET += tb/*.pb
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CLEAN_TARGET += tb/*.vcd
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CLEAN_TARGET += tb/*.wdb
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CLEAN_TARGET += tb/dcv.
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CLEAN_TARGET += tb/vsim.wlf
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CLEAN_TARGET += tb/work
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CLEAN_TARGET += tb/vcd
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CLEAN_TARGET += tb/run
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CLEAN_TARGET += tb/libraries
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CLEAN_TARGET += tb/.Xil
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CLEAN_TARGET += tb/xsim_gui_cmd.tcl
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CLEAN_TARGET += tb/libraries
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2018-03-23 11:55:11 +00:00
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2022-07-12 11:06:15 +00:00
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GENERIC_DEPS += $(HDL_LIBRARY_PATH)../scripts/adi_env.tcl
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2018-03-23 11:55:11 +00:00
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2023-12-14 17:27:23 +00:00
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.PHONY: all intel xilinx clean clean-all
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2018-03-23 11:55:11 +00:00
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2018-08-13 13:59:02 +00:00
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all: intel xilinx
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2018-03-23 11:55:11 +00:00
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clean: clean-all
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clean-all:
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2018-03-25 07:21:37 +00:00
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$(call clean, \
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2023-12-14 17:27:23 +00:00
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$(CLEAN_TARGET) .lock, \
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2018-03-25 07:21:37 +00:00
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$(HL)$(LIBRARY_NAME)$(NC) library)
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2018-03-23 11:55:11 +00:00
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2018-08-13 13:59:02 +00:00
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ifneq ($(INTEL_DEPS),)
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2018-03-27 09:21:09 +00:00
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2018-08-13 13:59:02 +00:00
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INTEL_DEPS += $(GENERIC_DEPS)
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INTEL_DEPS += $(HDL_LIBRARY_PATH)scripts/adi_ip_intel.tcl
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2023-12-14 17:27:23 +00:00
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_INTEL_LIB_DEPS = $(foreach dep,$(INTEL_LIB_DEPS),$(HDL_LIBRARY_PATH)$(dep)/.timestamp_intel)
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2018-03-27 09:21:09 +00:00
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2023-12-14 17:27:23 +00:00
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intel: .timestamp_intel
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2018-03-27 09:21:09 +00:00
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2023-12-14 17:27:23 +00:00
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.timestamp_intel: $(INTEL_DEPS) $(_INTEL_LIB_DEPS)
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2018-03-27 09:21:09 +00:00
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touch $@
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2023-12-14 17:27:23 +00:00
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$(_INTEL_LIB_DEPS):
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$(MAKE) -C $(dir $@) intel
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2018-03-27 09:21:09 +00:00
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endif
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ifneq ($(XILINX_DEPS),)
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XILINX_DEPS += $(GENERIC_DEPS)
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2018-08-13 13:59:02 +00:00
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XILINX_DEPS += $(HDL_LIBRARY_PATH)scripts/adi_ip_xilinx.tcl
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2023-12-14 17:27:23 +00:00
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_XILINX_LIB_DEPS = $(foreach dep,$(XILINX_LIB_DEPS),$(HDL_LIBRARY_PATH)$(dep)/component.xml)
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_XILINX_INTF_DEPS = $(foreach dep,$(XILINX_INTERFACE_DEPS),$(HDL_LIBRARY_PATH)$(dep))
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xilinx: component.xml
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2018-03-27 09:21:09 +00:00
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2023-12-14 17:27:23 +00:00
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.DELETE_ON_ERROR:
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2018-03-27 09:21:09 +00:00
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2023-12-14 17:27:23 +00:00
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component.xml: $(XILINX_DEPS) $(_XILINX_INTF_DEPS) $(_XILINX_LIB_DEPS)
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2018-03-23 11:55:11 +00:00
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-rm -rf $(CLEAN_TARGET)
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2018-03-25 07:21:37 +00:00
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$(call build, \
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$(VIVADO) $(LIBRARY_NAME)_ip.tcl, \
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$(LIBRARY_NAME)_ip.log, \
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$(HL)$(LIBRARY_NAME)$(NC) library)
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2018-03-23 11:55:11 +00:00
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2023-12-14 17:27:23 +00:00
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$(_XILINX_INTF_DEPS):
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$(MAKE) -C $(dir $@) $(notdir $@)
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$(_XILINX_LIB_DEPS):
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flock $(dir $@).lock -c "$(MAKE) -C $(dir $@) xilinx"; exit $$?
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%.xml:
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$(MAKE) -C $(dir $@) $(notdir $@)
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2018-03-27 09:21:09 +00:00
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endif
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