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pluto_hdl_adi/projects/ad9208_dual_ebz/vcu118/system_project.tcl

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Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
scripts: Merge adi_env.tcl into a single file Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-07-12 11:06:15 +00:00
source ../../../scripts/adi_env.tcl
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2018-08-14 08:43:32 +00:00
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
ad9208_dual_ebz: Initial version This commit add support for the dual AD9208-DUAL-EBZ board. The clocking scheme is different from the other projects. The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK), it is received directly from the clockchip SCLKOUT9 output through the REFCLK1. This is needed for deterministic latency where SYSREF must be sampled with the device clock by meeting setup and hold time. The two channels from each converter are merged together and transferred to the DDR with a single DMA. It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL. REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC board.
2019-04-04 15:16:11 +00:00
source $ad_hdl_dir/projects/scripts/adi_board.tcl
Merge pull request #430 from analogdevicesinc/update_tcl Rename projects for consistency
2020-02-06 14:32:40 +00:00
adi_project ad9208_dual_ebz_vcu118
adi_project_files ad9208_dual_ebz_vcu118 [list \
ad9208_dual_ebz: Initial version This commit add support for the dual AD9208-DUAL-EBZ board. The clocking scheme is different from the other projects. The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK), it is received directly from the clockchip SCLKOUT9 output through the REFCLK1. This is needed for deterministic latency where SYSREF must be sampled with the device clock by meeting setup and hold time. The two channels from each converter are merged together and transferred to the DDR with a single DMA. It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL. REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC board.
2019-04-04 15:16:11 +00:00
"system_top.v" \
"system_constr.xdc"\
library: Move ad_iobuf to the common library, as it's not Xilinx specific Updated all system_project and Makefiles
2020-09-23 08:30:18 +00:00
"$ad_hdl_dir/library/common/ad_iobuf.v" \
ad9208_dual_ebz: Initial version This commit add support for the dual AD9208-DUAL-EBZ board. The clocking scheme is different from the other projects. The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK), it is received directly from the clockchip SCLKOUT9 output through the REFCLK1. This is needed for deterministic latency where SYSREF must be sampled with the device clock by meeting setup and hold time. The two channels from each converter are merged together and transferred to the DDR with a single DMA. It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL. REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC board.
2019-04-04 15:16:11 +00:00
"$ad_hdl_dir/projects/daq3/common/daq3_spi.v" \
"$ad_hdl_dir/projects/common/vcu118/vcu118_system_constr.xdc" ]
## To improve timing in DDR4 MIG
#set_property strategy Performance_Retiming [get_runs impl_1]
set_property strategy Performance_SpreadSLLs [get_runs impl_1]
Merge pull request #430 from analogdevicesinc/update_tcl Rename projects for consistency
2020-02-06 14:32:40 +00:00
adi_project_run ad9208_dual_ebz_vcu118
ad9208_dual_ebz: Initial version This commit add support for the dual AD9208-DUAL-EBZ board. The clocking scheme is different from the other projects. The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK), it is received directly from the clockchip SCLKOUT9 output through the REFCLK1. This is needed for deterministic latency where SYSREF must be sampled with the device clock by meeting setup and hold time. The two channels from each converter are merged together and transferred to the DDR with a single DMA. It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL. REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC board.
2019-04-04 15:16:11 +00:00