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pluto_hdl_adi/library/axi_ad9361/axi_ad9361_rx.v

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Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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// ***************************************************************************
// ***************************************************************************
Add/edit copyright and license for .v, .sv files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
license: Add some clarification to the header license
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// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
license: Fix a spelling mistake
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// freedoms and responsibilities that he or she has by using this source/core.
license: Add some clarification to the header license
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//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
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//
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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// 1. The GNU General Public License version 2 as published by the
license: Add some clarification to the header license
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// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
// OR
//
license: Add some clarification to the header license
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// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
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//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
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module axi_ad9361_rx #(
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// parameters
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parameter ID = 0,
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
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parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
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parameter MODE_1R1T = 0,
axi_ad9361: Update the PPS receiver module + Add a HDL parameter for the PPS receiver module : PPS_RECEIVER_ENABLE. By default the module is disabled. + Add the CMOS_OR_LVDS_N and PPS_RECEIVER_ENABLE into the CONFIG register + Define a pps_status read only register, which will be asserted, if the free running counter reach a certain fixed threshold. (2^28) The register can be deasserted by an incomming PPS only.
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parameter CMOS_OR_LVDS_N = 0,
parameter PPS_RECEIVER_ENABLE = 0,
axi_ad9361- add receive init delay
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parameter INIT_DELAY = 0,
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parameter USERPORTS_DISABLE = 0,
parameter DATAFORMAT_DISABLE = 0,
parameter DCFILTER_DISABLE = 0,
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
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parameter IQCORRECTION_DISABLE = 0
) (
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library/axi_ad9361: mmcm rst for plls
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// common
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output mmcm_rst,
library/axi_ad9361: mmcm rst for plls
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// adc interface
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output adc_rst,
input adc_clk,
input adc_valid,
input [47:0] adc_data,
input adc_status,
output adc_r1_mode,
output adc_ddr_edgesel,
input [47:0] dac_data,
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// delay interface
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output [12:0] up_dld,
output [64:0] up_dwdata,
input [64:0] up_drdata,
input delay_clk,
output delay_rst,
input delay_locked,
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// dma interface
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output adc_enable_i0,
output adc_valid_i0,
output [15:0] adc_data_i0,
output adc_enable_q0,
output adc_valid_q0,
output [15:0] adc_data_q0,
output adc_enable_i1,
output adc_valid_i1,
output [15:0] adc_data_i1,
output adc_enable_q1,
output adc_valid_q1,
output [15:0] adc_data_q1,
input adc_dovf,
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// gpio
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input [31:0] up_adc_gpio_in,
output [31:0] up_adc_gpio_out,
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axi_ad9361: ad_pps_receiver integration The ad_pps_receiver is instantiated at the top of core. The rcounter is placed into adc/dac_common registers space, at the address 0x30 (word aligned). The interrupt mask is placed into adc/dac_common, at the address 0x04 (word aligned). Because the core has an instance of both modules, the interrupt masks are OR-ed together.
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// 1PPS reporting counter and interrupt
input [31:0] up_pps_rcounter,
axi_ad9361: Update the PPS receiver module + Add a HDL parameter for the PPS receiver module : PPS_RECEIVER_ENABLE. By default the module is disabled. + Add the CMOS_OR_LVDS_N and PPS_RECEIVER_ENABLE into the CONFIG register + Define a pps_status read only register, which will be asserted, if the free running counter reach a certain fixed threshold. (2^28) The register can be deasserted by an incomming PPS only.
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input up_pps_status,
axi_ad9361: ad_pps_receiver integration The ad_pps_receiver is instantiated at the top of core. The rcounter is placed into adc/dac_common registers space, at the address 0x30 (word aligned). The interrupt mask is placed into adc/dac_common, at the address 0x04 (word aligned). Because the core has an instance of both modules, the interrupt masks are OR-ed together.
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output up_pps_irq_mask,
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// processor interface
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input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
axi_ad9361: Add DRP connection to the interface module
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output up_rack,
// drp interface
output up_drp_sel,
output up_drp_wr,
output [11:0] up_drp_addr,
output [31:0] up_drp_wdata,
input [31:0] up_drp_rdata,
input up_drp_ready,
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
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input up_drp_locked
);
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// configuration settings
axi_ad9361: Update the PPS receiver module + Add a HDL parameter for the PPS receiver module : PPS_RECEIVER_ENABLE. By default the module is disabled. + Add the CMOS_OR_LVDS_N and PPS_RECEIVER_ENABLE into the CONFIG register + Define a pps_status read only register, which will be asserted, if the free running counter reach a certain fixed threshold. (2^28) The register can be deasserted by an incomming PPS only.
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localparam CONFIG = (PPS_RECEIVER_ENABLE * 256) +
(CMOS_OR_LVDS_N * 128) +
(MODE_1R1T * 16) +
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(USERPORTS_DISABLE * 8) +
(DATAFORMAT_DISABLE * 4) +
(DCFILTER_DISABLE * 2) +
(IQCORRECTION_DISABLE * 1);
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// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
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reg [31:0] up_rdata_int = 'd0;
reg up_rack_int = 'd0;
reg up_wack_int = 'd0;
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// internal signals
wire [15:0] adc_dcfilter_data_out_0_s;
wire [15:0] adc_dcfilter_data_out_1_s;
wire [15:0] adc_dcfilter_data_out_2_s;
wire [15:0] adc_dcfilter_data_out_3_s;
wire [ 3:0] up_adc_pn_err_s;
wire [ 3:0] up_adc_pn_oos_s;
wire [ 3:0] up_adc_or_s;
wire [31:0] up_rdata_s[0:5];
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wire [ 5:0] up_rack_s;
wire [ 5:0] up_wack_s;
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// processor read interface
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assign up_wack = up_wack_int;
assign up_rack = up_rack_int;
assign up_rdata = up_rdata_int;
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always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
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up_rdata_int <= 'd0;
up_rack_int <= 'd0;
up_wack_int <= 'd0;
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end else begin
up_status_pn_err <= | up_adc_pn_err_s;
up_status_pn_oos <= | up_adc_pn_oos_s;
up_status_or <= | up_adc_or_s;
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up_rdata_int <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
up_rack_int <= | up_rack_s;
up_wack_int <= | up_wack_s;
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end
end
// channel 0 (i)
axi_ad9361_rx_channel #(
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.Q_OR_I_N (0),
.CHANNEL_ID (0),
.DISABLE (0),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-04-08 10:21:52 +00:00
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_rx_channel_0 (
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.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
.adc_data (adc_data[11:0]),
.adc_data_q (adc_data[23:12]),
.adc_or (1'b0),
.dac_data (dac_data[11:0]),
.adc_dcfilter_data_out (adc_dcfilter_data_out_0_s),
.adc_dcfilter_data_in (adc_dcfilter_data_out_1_s),
.adc_iqcor_valid (adc_valid_i0),
.adc_iqcor_data (adc_data_i0),
.adc_enable (adc_enable_i0),
.up_adc_pn_err (up_adc_pn_err_s[0]),
.up_adc_pn_oos (up_adc_pn_oos_s[0]),
.up_adc_or (up_adc_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// channel 1 (q)
axi_ad9361_rx_channel #(
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.Q_OR_I_N (1),
.CHANNEL_ID (1),
.DISABLE (0),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
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.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_rx_channel_1 (
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.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
.adc_data (adc_data[23:12]),
.adc_data_q (adc_data[11:0]),
.adc_or (1'b0),
.dac_data (dac_data[23:12]),
.adc_dcfilter_data_out (adc_dcfilter_data_out_1_s),
.adc_dcfilter_data_in (adc_dcfilter_data_out_0_s),
.adc_iqcor_valid (adc_valid_q0),
.adc_iqcor_data (adc_data_q0),
.adc_enable (adc_enable_q0),
.up_adc_pn_err (up_adc_pn_err_s[1]),
.up_adc_pn_oos (up_adc_pn_oos_s[1]),
.up_adc_or (up_adc_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// channel 2 (i)
axi_ad9361_rx_channel #(
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.Q_OR_I_N (0),
.CHANNEL_ID (2),
.DISABLE (MODE_1R1T),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
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.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_rx_channel_2 (
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.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
.adc_data (adc_data[35:24]),
.adc_data_q (adc_data[47:36]),
.adc_or (1'b0),
.dac_data (dac_data[35:24]),
.adc_dcfilter_data_out (adc_dcfilter_data_out_2_s),
.adc_dcfilter_data_in (adc_dcfilter_data_out_3_s),
.adc_iqcor_valid (adc_valid_i1),
.adc_iqcor_data (adc_data_i1),
.adc_enable (adc_enable_i1),
.up_adc_pn_err (up_adc_pn_err_s[2]),
.up_adc_pn_oos (up_adc_pn_oos_s[2]),
.up_adc_or (up_adc_or_s[2]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// channel 3 (q)
axi_ad9361_rx_channel #(
ad9361- adc data path split
2016-09-23 17:42:14 +00:00
.Q_OR_I_N (1),
.CHANNEL_ID (3),
.DISABLE (MODE_1R1T),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-04-08 10:21:52 +00:00
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_rx_channel_3 (
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
.adc_data (adc_data[47:36]),
.adc_data_q (adc_data[35:24]),
.adc_or (1'b0),
.dac_data (dac_data[47:36]),
.adc_dcfilter_data_out (adc_dcfilter_data_out_3_s),
.adc_dcfilter_data_in (adc_dcfilter_data_out_2_s),
.adc_iqcor_valid (adc_valid_q1),
.adc_iqcor_data (adc_data_q1),
.adc_enable (adc_enable_q1),
.up_adc_pn_err (up_adc_pn_err_s[3]),
.up_adc_pn_oos (up_adc_pn_oos_s[3]),
.up_adc_or (up_adc_or_s[3]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// common processor control
ad9361- adc data path split
2016-09-23 17:42:14 +00:00
up_adc_common #(
.ID (ID),
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
ad9361- adc data path split
2016-09-23 17:42:14 +00:00
.CONFIG (CONFIG),
.DRP_DISABLE (1),
axi_*: Fix instantiation of up_[adc|dac]_[common|channel] A couple of new parameters and new ports are missing in several up_[adc|dac]_[common|channel] instance, and generates warnings. The rule of thumb is to use full instantiations, defining all the existing parameter and ports of the module. Fix all the instantiation of up_[adc|dac]_[common|channel], by defining all its parameters and ports.
2018-02-16 09:57:48 +00:00
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.GPIO_DISABLE (0),
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-04-08 10:21:52 +00:00
.START_CODE_DISABLE (0)
) i_up_adc_common (
library/axi_ad9361: mmcm rst for plls
2016-05-04 17:39:26 +00:00
.mmcm_rst (mmcm_rst),
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (adc_r1_mode),
.adc_ddr_edgesel (adc_ddr_edgesel),
.adc_pin_mode (),
.adc_status (adc_status),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
axi adc cores: Add missing ports to up_adc_common instance
2017-05-12 10:39:05 +00:00
.adc_sref_sync (),
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
.adc_sync (),
up_adc_common: Update IPs and adi_regmap_adc definition file to latest up_adc_common module
2022-09-29 05:26:51 +00:00
.adc_ext_sync_arm (),
.adc_ext_sync_disarm (),
.adc_ext_sync_manual_req (),
axi_ad9361: Fix missing connection warnings
2020-09-10 06:10:14 +00:00
.adc_num_lanes (),
up_adc_common: Update IPs and adi_regmap_adc definition file to latest up_adc_common module
2022-09-29 05:26:51 +00:00
.adc_custom_control (),
.adc_crc_enable (),
axi_ad9361: Fix missing connection warnings
2020-09-10 06:10:14 +00:00
.adc_sdr_ddr_n (),
up_adc_common: Update IPs and adi_regmap_adc definition file to latest up_adc_common module
2022-09-29 05:26:51 +00:00
.adc_symb_op (),
.adc_symb_8_16b (),
axi adc cores: Add missing ports to up_adc_common instance
2017-05-12 10:39:05 +00:00
.up_adc_ce (),
axi_ad9361: ad_pps_receiver integration The ad_pps_receiver is instantiated at the top of core. The rcounter is placed into adc/dac_common registers space, at the address 0x30 (word aligned). The interrupt mask is placed into adc/dac_common, at the address 0x04 (word aligned). Because the core has an instance of both modules, the interrupt masks are OR-ed together.
2017-07-28 06:57:13 +00:00
.up_pps_rcounter (up_pps_rcounter),
axi_ad9361: Update the PPS receiver module + Add a HDL parameter for the PPS receiver module : PPS_RECEIVER_ENABLE. By default the module is disabled. + Add the CMOS_OR_LVDS_N and PPS_RECEIVER_ENABLE into the CONFIG register + Define a pps_status read only register, which will be asserted, if the free running counter reach a certain fixed threshold. (2^28) The register can be deasserted by an incomming PPS only.
2017-08-02 15:31:46 +00:00
.up_pps_status (up_pps_status),
axi_ad9361: ad_pps_receiver integration The ad_pps_receiver is instantiated at the top of core. The rcounter is placed into adc/dac_common registers space, at the address 0x30 (word aligned). The interrupt mask is placed into adc/dac_common, at the address 0x04 (word aligned). Because the core has an instance of both modules, the interrupt masks are OR-ed together.
2017-07-28 06:57:13 +00:00
.up_pps_irq_mask (up_pps_irq_mask),
axi_ad9361: Fix missing connection warnings
2020-09-10 06:10:14 +00:00
.up_adc_r1_mode (),
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
axi_ad9361: Add DRP connection to the interface module
2016-10-11 13:38:42 +00:00
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked),
Update IPs based on up_adc_common changes
2023-01-12 09:10:23 +00:00
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
up_adc_common- port name changes
2017-05-10 18:45:17 +00:00
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd3),
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
.up_adc_gpio_in (up_adc_gpio_in),
.up_adc_gpio_out (up_adc_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[4]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[4]),
.up_rack (up_rack_s[4]));
// adc delay control
ad9361- adc data path split
2016-09-23 17:42:14 +00:00
up_delay_cntrl #(
axi_ad9361- add receive init delay
2017-03-13 20:28:38 +00:00
.INIT_DELAY (INIT_DELAY),
ad9361- adc data path split
2016-09-23 17:42:14 +00:00
.DATA_WIDTH (13),
libraries: Update modules according to guideline * Added header license for the files that didn't have * Modified parentheses * Removed extra spaces at the end of lines * Fixed parameters list to be each parameter on its line * Deleted lines after endmodule and consecutive empty lines * Fixed indentation Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-04-08 10:21:52 +00:00
.BASE_ADDRESS (6'h02)
) i_delay_cntrl (
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),
.up_dld (up_dld),
.up_dwdata (up_dwdata),
.up_drdata (up_drdata),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[5]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[5]),
.up_rack (up_rack_s[5]));
endmodule