375 lines
14 KiB
ReStructuredText
375 lines
14 KiB
ReStructuredText
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.. _ad4630_fmc:
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AD4630-FMC HDL project
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=================================================================================
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Overview
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---------------------------------------------------------------------------------
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The :adi:`AD4630-24` is a two-channel, simultaneous sampling, Easy Drive, 2 MSPS
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successive approximation register (SAR) analog-to-digital converter (ADC). The
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:adi:`AD4030-24` is the single channel version. With a guaranteed maximum ±0.9
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ppm INL and no missing codes at 24-bits, the :adi:`AD4630-24` and
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:adi:`AD4030-24` achieve unparalleled precision from −40°C to +125°C.
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The :adi:`AD4030-16` is a 16-bit dual channel version.
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A low-drift, internal precision reference buffer eases voltage reference
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sharing with other system circuitry. The AD4630-24 offers a typical dynamic
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range of 106 dB when using a 5 V reference. The :adi:`AD4030-24` offers a typical
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dynamic range of 109 dB using a 5 V reference. The low noise floor enables signal
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chains requiring less gain and lower power. A block averaging filter with
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programmable decimation ratio can increase dynamic range up to 153 dB and
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155.5dB for the :adi:`AD4030`. The wide differential input and common mode ranges
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allow inputs to use the full ±VREF range without saturating, simplifying signal
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conditioning requirements and system calibration. The improved settling of the
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Easy Drive analog inputs broadens the selection of analog front-end components
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compatible with the :adi:`AD4630-24`, :adi:`AD4630-16` and :adi:`AD4030-24`.
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Both single-ended and differential signals are supported.
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The versatile Flexi-SPI serial interface eases host processor and ADC
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integration. A wide data clocking window, multiple SDO lanes, and optional DDR
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data clocking can reduce the serial clock to 10 MHz while operating at a
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sample rate of 2 MSPS. Echo clock mode and ADC master clock mode relax the
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timing requirements and simplify the use of digital isolators.
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The :adi:`AD4630-24`'s, :adi:`AD4630-16`'s and :adi:`AD4030-24`'s BGA package
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integrates all critical power supply and reference bypass capacitors, reducing
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the footprint and system component count, and lessening sensitivity to board
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layout.
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The HDL reference design for the :adi:`EVAL-AD4630_FMCZ` and
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:adi:`EVAL-AD4030_FMCZ` provides all the interfaces that are necessary to
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interact with the device using a Xilinx FPGA development board. The design has
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all the necessary infrastructure to acquire data from the :adi:`AD4630-24`
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24-bit dual-channel precision SAR ADC, :adi:`AD4630-16` 16-bit dual channel
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precision SAR ADC and :adi:`AD4030-24` single channel ADC, supporting
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continuous data capture at maximum 2 MSPS data rate. The design targeted to the
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Zedboard, which is a low cost FPGA carrier board from Digilent, using a
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Zynq-7000 re-programmable SoC from Xilinx.
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Applications:
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* Automatic test equipment
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* Digital control loops
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* Medical instrumentation
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* Seismology
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* Semiconductor manufacturing
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* Scientific instrumentation
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Supported boards
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-------------------------------------------------------------------------------
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- :adi:`EVAL-AD4030-24FMCZ <EVAL-AD4030-24FMCZ>`
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- :adi:`EVAL-AD4630-16FMCZ <EVAL-AD4630-16FMCZ>`
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- :adi:`EVAL-AD4630-24FMCZ <EVAL-AD4630-24FMCZ>`
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Supported devices
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-------------------------------------------------------------------------------
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- :adi:`AD4030-24`
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- :adi:`AD4630-16`
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- :adi:`AD4630-24`
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Supported carriers
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-------------------------------------------------------------------------------
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- :xilinx:`ZedBoard <products/boards-and-kits/1-8dyf-11.html>` on FMC slot
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Block design
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---------------------------------------------------------------------------------
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The reference design uses the :ref:`SPI Engine Framework <spi_engine>` to
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interface with the AD4630 ADC. The design supports almost all possible digital
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interface configurations of the device. In echo clock mode, because the clock
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for data latching is routed back through the BUSY line, an additional data
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capture module is used for saving the received samples and transmitting
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forward for the DMA.
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There are three modes in which the system can run. Refer to the :adi:`AD4630-24`,
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:adi:`AD4630-16` or :adi:`AD4030-24` data sheet section titled SAMPLE CONVERSION
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TIMING AND DATA TRANSFER for more explanation of data transfer zones.
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The data path and clock domains are depicted in the below diagrams:
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SPI mode - transfer zone 1
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The main aspect of this mode is the fact that it is using the BUSY signal from
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the ADC to trigger the Offload module. Data is then clocked out by the
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Execution module and transferred to the DMA by the Offload module. CNV is
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always generated by the AXI PWM GEN IP core regardless of the mode. Zone 1
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transfer is not currently supported by the pre-compiled HDL files that are
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included in the SD card image that is provided with the evaluation board.
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.. image:: ad463x_hdl_cm0_cz1_1.svg
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:width: 800
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:align: center
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:alt: AD4630_FMC SPI mode - transfer zone 1 block diagram
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SPI mode - transfer zone 2
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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In this mode, the BUSY signal is not used and both the CNV and the Offload
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trigger signals are generated by the AXI PWM GEN core. The reason for using two
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PWM outputs instead of a common one is to accommodate for the averaging mode
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where the two signals will have different frequencies.
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.. image:: ad463x_hdl_cm0_cz2_1.svg
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:width: 800
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:align: center
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:alt: AD4630_FMC SPI mode - transfer zone 2 block diagram
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Echo clock mode - transfer zone 2
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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In this configuration, the ADC's BUSY-SCKOUT pin functions as a bit-clock
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output and is generated by looping-through the host’s SCK. The SPI engine is
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driving the SPI signals except it is no longer reading the data. For this
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purpose, the Data Capture IP is used. This also allows for reading data in DDR
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mode.
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.. image:: ad463x_hdl_cm1_cz2_1.svg
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:width: 800
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:align: center
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:alt: AD4630_FMC Echo clock mode - transfer zone 2 block diagram
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The design supports the following interface and clock modes both in SDR and DDR:
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================== ================== ================== ==================
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Mode 1 Lane per channel 2 Lane per channel 4 lane per channel
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================== ================== ================== ==================
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SPI mode yes yes yes
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Echo Clock mode yes yes yes
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================== ================== ================== ==================
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Configuration modes
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The CLK_MODE configuration parameter defines clocking mode of the device's
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digital interface: Options: 0 - SPI mode, 1 - Echo-clock or Master clock mode
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The NUM_OF_SDI configutation parameter defines the number of MOSI lines of the
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SPI interface: Options: 1 - Interleaved mode, 2 - 1 lane per channel,
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4 - 2 lanes per channel, 8 - 4 lanes per channel
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The CAPTURE_ZONE configuration parameter defines the capture zone of the next
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sample. There are two capture zones: 1 - from negative edge of the BUSY line
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until the next CNV positive edge -20ns, 2 - from the next consecutive CNV
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positive edge +20ns until the second next consecutive CNV positive edge -20ns
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The DDR_EN configuration parameter defines the type of data transfer. In echo
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and master clock mode the SDI lines can have Single or Double Data Rates.
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Options: 0 - MISO runs on SDR, 1 - MISO runs on DDR.
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL(see more at :ref:`architecture`).
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======================== ===========
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Instance Address
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======================== ===========
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spi_ad463x_axi_regmap 0x44A0_0000
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axi_ad463x_dma 0x44A3_0000
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spi_clkgen 0x44A7_0000
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cnv_generator 0x44B0_0000
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======================== ===========
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I2C connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 20 20 20 20 20
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:header-rows: 1
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* - I2C type
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- I2C manager instance
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- Alias
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- Address
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- I2C subordinate
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* - PL
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- iic_fmc
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- axi_iic_fmc
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- 0x4162_0000
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- ---
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* - PL
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- iic_main
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- axi_iic_main
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- 0x4160_0000
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- ---
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SPI connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 1
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* - SPI type
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- SPI manager instance
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- SPI subordinate
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- CS
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* - PL
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- axi_spi_engine
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- ad4630
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- 0
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GPIOs
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The Software GPIO number is calculated as follows:
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- Zynq-7000: if PS7 is used, then offset is 54
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 2
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* - GPIO signal
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- Direction
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- HDL GPIO EMIO
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- Software GPIO
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* -
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- (from FPGA view)
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-
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- Zynq-7000
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* - ad463x_resetn
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- INOUT
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- 32
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- 86
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Below are the Programmable Logic interrupts used in this project.
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=================== === ========== ===========
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Instance name HDL Linux Zynq Actual Zynq
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=================== === ========== ===========
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axi_ad463x_dma 13 57 89
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spi_ad463x 12 56 88
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=================== === ========== ===========
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Building the HDL project
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-------------------------------------------------------------------------------
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The design is built upon ADI's generic HDL reference design framework.
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ADI does not distribute the bit/elf files of these projects so they
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must be built from the sources available :git-hdl:`here </>`. To get
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the source you must
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`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the HDL repository, and then build the project as follows:.
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**Linux/Cygwin/WSL**
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.. code-block::
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:linenos:
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user@analog:~$ cd hdl/projects/ad4630_fmc/zed
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user@analog:~/hdl/projects/ad4630_fmc/zed$ make NUM_OF_SDI=4 CAPTURE_ZONE=2
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The result of the build, if parameters were used, will be in a folder named
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by the configuration used:
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if the following command was run
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``make NUM_OF_SDI=4 CAPTURE_ZONE=2``
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then the folder name will be:
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``NUMOFSDI4_CAPTUREZONE2``
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A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
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Resources
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-------------------------------------------------------------------------------
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Systems related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :dokuwiki:`[Wiki] AD463X and AD403X Developer's Guide <resources/eval/ad4630-24-eval-board/ad4630-24-developer-guide>`
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Hardware related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Product datasheets:
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- :adi:`AD4030-24`
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- :adi:`AD4630-16`
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- :adi:`AD4630-24`
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- :dokuwiki:`[Wiki] AD4630/AD4030 Evaluation Board User Guide <resources/eval/ad4630-24-eval-board>`
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HDL related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-hdl:`AD4630_FMC HDL project source code <projects/ad4630_fmc>`
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- :dokuwiki:`[Wiki] AD4630_FMC HDL project documentation <resources/eval/user-guides/ad463x/hdl>`
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.. list-table::
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:widths: 30 35 35
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:header-rows: 1
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* - IP name
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- Source code link
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- Documentation link
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* - AD463X_DATA_CAPTURE
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- :git-hdl:`library/ad463x_data_capture`
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- ---
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* - AXI_CLKGEN
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- :git-hdl:`library/axi_clkgen`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_clkgen>`
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* - AXI_DMAC
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- :git-hdl:`library/axi_dmac`
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- :ref:`here <axi_dmac>`
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* - AXI_HDMI_TX
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- :git-hdl:`library/axi_hdmi_tx`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_hdmi_tx>`
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* - AXI_I2S_ADI
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- :git-hdl:`library/axi_i2s_adi`
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- ---
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* - AXI_PWM_GEN
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- :git-hdl:`library/axi_pwm_gen`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_pwm_gen>`
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* - AXI_SPDIF_TX
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- :git-hdl:`library/axi_spdif_tx`
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- ---
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* - AXI_SPI_ENGINE
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- :git-hdl:`library/spi_engine/axi_spi_engine`
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- :ref:`here <spi_engine axi>`
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* - SPI_AXIS_REORDER
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- :git-hdl:`library/spi_engine/spi_axis_reorder`
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- ---
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* - SPI_ENGINE_EXECUTION
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- :git-hdl:`library/spi_engine/spi_engine_execution`
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- :ref:`here <spi_engine execution>`
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* - SPI_ENGINE_INTERCONNECT
|
|||
|
|
- :git-hdl:`library/spi_engine/spi_engine_interconnect`
|
|||
|
|
- :ref:`here <spi_engine interconnect>`
|
|||
|
|
* - SPI_ENGINE_OFFLOAD
|
|||
|
|
- :git-hdl:`library/spi_engine/spi_engine_offload`
|
|||
|
|
- :ref:`here <spi_engine offload>`
|
|||
|
|
* - SYSID_ROM
|
|||
|
|
- :git-hdl:`library/sysid_rom`
|
|||
|
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
|
|||
|
|
* - UTIL_I2C_MIXER
|
|||
|
|
- :git-hdl:`library/util_i2c_mixer <library/util_i2c_mixer>`
|
|||
|
|
- ---
|
|||
|
|
|
|||
|
|
- :ref:`SPI Engine Framework documentation <spi_engine>`
|
|||
|
|
|
|||
|
|
Software related
|
|||
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|||
|
|
|
|||
|
|
- :git-linux:`AD4630_FMC Linux driver source code <analogdevicesinc/linux/blob/main/drivers/iio/adc/ad4630.c>`
|
|||
|
|
- :git-no-os:`AD463x_FMC No-OS project source code <projects/ad463x_fmcz>`
|
|||
|
|
- :dokuwiki:`AD4630 ADC Linux Driver <resources/tools-software/linux-drivers/iio-adc/ad4630>`
|
|||
|
|
- :dokuwiki:`AD463X ADC Linux Driver <resources/tools-software/linux-drivers/iio-adc/ad463x>`
|
|||
|
|
- :dokuwiki:`AD4630/AD4030 - No-OS Driver <resources/tools-software/uc-drivers/ad463x>`
|
|||
|
|
|
|||
|
|
.. include:: ../common/more_information.rst
|
|||
|
|
|
|||
|
|
.. include:: ../common/support.rst
|