233 lines
10 KiB
Tcl
233 lines
10 KiB
Tcl
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###############################################################################
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## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# TX parameters
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set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L
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set TX_NUM_OF_CONVERTERS $ad_project_params(TX_JESD_M) ; # M
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set TX_SAMPLES_PER_FRAME $ad_project_params(TX_JESD_S) ; # S
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set TX_SAMPLE_WIDTH 16 ; # N/NP
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set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
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# RX parameters
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set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L
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set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M
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set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S) ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
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set dac_fifo_name axi_adrv9026_dacfifo
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set dac_data_width [expr 32*$TX_NUM_OF_LANES]
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set dac_dma_data_width 128
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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# adrv9026
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create_bd_port -dir I dac_fifo_bypass
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create_bd_port -dir I core_clk
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# dac peripherals
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ad_ip_instance axi_adxcvr axi_adrv9026_tx_xcvr
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ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.QPLL_ENABLE 1
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ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.TX_OR_RX_N 1
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ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.SYS_CLK_SEL 3
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ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.OUT_CLK_SEL 3
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adi_axi_jesd204_tx_create axi_adrv9026_tx_jesd $TX_NUM_OF_LANES
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ad_ip_instance util_upack2 util_adrv9026_tx_upack [list \
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NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_tx_create tx_adrv9026_tpl_core $TX_NUM_OF_LANES \
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$TX_NUM_OF_CONVERTERS \
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$TX_SAMPLES_PER_FRAME \
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$TX_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_adrv9026_tx_dma
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_TYPE_DEST 1
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.CYCLIC 1
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.MAX_BYTES_PER_BURST 256
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.FIFO_SIZE 32
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ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
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# adc peripherals
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ad_ip_instance axi_adxcvr axi_adrv9026_rx_xcvr
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ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.TX_OR_RX_N 0
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ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.SYS_CLK_SEL 0
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ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.OUT_CLK_SEL 3
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adi_axi_jesd204_rx_create axi_adrv9026_rx_jesd $RX_NUM_OF_LANES
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ad_ip_instance util_cpack2 util_adrv9026_rx_cpack [list \
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NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_rx_create rx_adrv9026_tpl_core $RX_NUM_OF_LANES \
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$RX_NUM_OF_CONVERTERS \
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$RX_SAMPLES_PER_FRAME \
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$RX_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_adrv9026_rx_dma
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_NUM_OF_LANES]
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.MAX_BYTES_PER_BURST 256
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.FIFO_SIZE 32
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# common cores
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ad_ip_instance util_adxcvr util_adrv9026_xcvr
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ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
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ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_RATE 10
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ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_RATE 10
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ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_OUT_DIV 1
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ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV 4
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ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV_4_5 5
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ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CLK25_DIV 10
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ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_CLK25_DIV 10
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ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_PMA_CFG 0x001E7080
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ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020
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ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_FBDIV 40
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ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_REFCLK_DIV 1
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ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_INVERT 6
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ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_INVERT 15
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# xcvr interfaces
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set tx_ref_clk tx_ref_clk_0
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set rx_ref_clk rx_ref_clk_0
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create_bd_port -dir I $tx_ref_clk
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create_bd_port -dir I $rx_ref_clk
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ad_connect $sys_cpu_resetn util_adrv9026_xcvr/up_rstn
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ad_connect $sys_cpu_clk util_adrv9026_xcvr/up_clk
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# Tx
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ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_tx_xcvr axi_adrv9026_tx_jesd {2 3 1 0} core_clk
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ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_0
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ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_0
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ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_4
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ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_4
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# Rx
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ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_rx_xcvr axi_adrv9026_rx_jesd {} core_clk
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for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} {
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set ch [expr $i]
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ad_xcvrpll $rx_ref_clk util_adrv9026_xcvr/cpll_ref_clk_$ch
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ad_xcvrpll axi_adrv9026_rx_xcvr/up_pll_rst util_adrv9026_xcvr/up_cpll_rst_$ch
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}
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# connections (dac)
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ad_connect core_clk tx_adrv9026_tpl_core/link_clk
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ad_connect axi_adrv9026_tx_jesd/tx_data tx_adrv9026_tpl_core/link
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ad_connect core_clk util_adrv9026_tx_upack/clk
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ad_connect core_clk_rstgen/peripheral_reset util_adrv9026_tx_upack/reset
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for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect tx_adrv9026_tpl_core/dac_enable_$i util_adrv9026_tx_upack/enable_$i
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ad_connect util_adrv9026_tx_upack/fifo_rd_data_$i tx_adrv9026_tpl_core/dac_data_$i
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}
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ad_connect tx_adrv9026_tpl_core/dac_valid_0 util_adrv9026_tx_upack/fifo_rd_en
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ad_connect core_clk axi_adrv9026_dacfifo/dac_clk
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ad_connect core_clk_rstgen/peripheral_reset axi_adrv9026_dacfifo/dac_rst
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ad_connect util_adrv9026_tx_upack/s_axis_valid VCC
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ad_connect util_adrv9026_tx_upack/s_axis_ready axi_adrv9026_dacfifo/dac_valid
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ad_connect util_adrv9026_tx_upack/s_axis_data axi_adrv9026_dacfifo/dac_data
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ad_connect core_clk axi_adrv9026_dacfifo/dma_clk
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ad_connect core_clk_rstgen/peripheral_reset axi_adrv9026_dacfifo/dma_rst
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ad_connect core_clk axi_adrv9026_tx_dma/m_axis_aclk
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ad_connect axi_adrv9026_dacfifo/dma_valid axi_adrv9026_tx_dma/m_axis_valid
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ad_connect axi_adrv9026_dacfifo/dma_data axi_adrv9026_tx_dma/m_axis_data
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ad_connect axi_adrv9026_dacfifo/dma_ready axi_adrv9026_tx_dma/m_axis_ready
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ad_connect axi_adrv9026_dacfifo/dma_xfer_req axi_adrv9026_tx_dma/m_axis_xfer_req
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ad_connect axi_adrv9026_dacfifo/dma_xfer_last axi_adrv9026_tx_dma/m_axis_last
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ad_connect axi_adrv9026_dacfifo/dac_dunf tx_adrv9026_tpl_core/dac_dunf
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ad_connect axi_adrv9026_dacfifo/bypass dac_fifo_bypass
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ad_connect core_clk_rstgen/peripheral_aresetn axi_adrv9026_tx_dma/m_src_axi_aresetn
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# connections (adc)
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ad_connect core_clk rx_adrv9026_tpl_core/link_clk
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ad_connect axi_adrv9026_rx_jesd/rx_sof rx_adrv9026_tpl_core/link_sof
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ad_connect axi_adrv9026_rx_jesd/rx_data_tdata rx_adrv9026_tpl_core/link_data
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ad_connect axi_adrv9026_rx_jesd/rx_data_tvalid rx_adrv9026_tpl_core/link_valid
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ad_connect core_clk util_adrv9026_rx_cpack/clk
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ad_connect core_clk_rstgen/peripheral_reset util_adrv9026_rx_cpack/reset
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for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect rx_adrv9026_tpl_core/adc_enable_$i util_adrv9026_rx_cpack/enable_$i
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ad_connect rx_adrv9026_tpl_core/adc_data_$i util_adrv9026_rx_cpack/fifo_wr_data_$i
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}
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ad_connect $sys_dma_resetn axi_adrv9026_rx_dma/m_dest_axi_aresetn
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ad_connect rx_adrv9026_tpl_core/adc_valid_0 util_adrv9026_rx_cpack/fifo_wr_en
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ad_connect rx_adrv9026_tpl_core/adc_dovf util_adrv9026_rx_cpack/fifo_wr_overflow
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ad_connect core_clk axi_adrv9026_rx_dma/fifo_wr_clk
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ad_connect util_adrv9026_rx_cpack/packed_fifo_wr axi_adrv9026_rx_dma/fifo_wr
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A00000 rx_adrv9026_tpl_core
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ad_cpu_interconnect 0x44A04000 tx_adrv9026_tpl_core
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ad_cpu_interconnect 0x44A80000 axi_adrv9026_tx_xcvr
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ad_cpu_interconnect 0x44A90000 axi_adrv9026_tx_jesd
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ad_cpu_interconnect 0x7c420000 axi_adrv9026_tx_dma
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ad_cpu_interconnect 0x44A60000 axi_adrv9026_rx_xcvr
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ad_cpu_interconnect 0x44AA0000 axi_adrv9026_rx_jesd
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ad_cpu_interconnect 0x7c400000 axi_adrv9026_rx_dma
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# gt uses hp0, and 100MHz clock for both DRP and AXI4
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ad_mem_hp0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HP0
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ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9026_rx_xcvr/m_axi
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# interconnect (mem/dac)
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ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9026_rx_dma/m_dest_axi
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ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9026_tx_dma/m_src_axi
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# interrupts
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ad_cpu_interrupt ps-10 mb-15 axi_adrv9026_tx_jesd/irq
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ad_cpu_interrupt ps-11 mb-14 axi_adrv9026_rx_jesd/irq
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ad_cpu_interrupt ps-13 mb-12 axi_adrv9026_tx_dma/irq
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ad_cpu_interrupt ps-14 mb-11 axi_adrv9026_rx_dma/irq
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