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pluto_hdl_adi/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc

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axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
axi_dacfifo: Fix constraints
2017-02-21 12:45:18 +00:00
set_property ASYNC_REG TRUE \
axi_dacfifo: Redesign the bypass functionality
2017-02-23 15:32:31 +00:00
[get_cells -hier *_xfer_req_m*] \
[get_cells -hier *_xfer_last_m*] \
[get_cells -hier *dac_xfer_out*] \
[get_cells -hier *dac_bypass_*] \
[get_cells -hier *dma_bypass_*]
axi_dacfifo: Update the constraints
2016-05-24 15:09:27 +00:00
axi_dacfifo: Redesign the bypass functionality
2017-02-23 15:32:31 +00:00
set_false_path -to [get_cells -hier -filter {name =~ *_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *_xfer_last_m_reg[0]* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *dac_xfer_out_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *_bypass_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *dma_rst_m1* && IS_SEQUENTIAL}]
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
axi_dacfifo: Redesign the bypass functionality
2017-02-23 15:32:31 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}]
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
axi_dacfifo: Redesign the bypass functionality
2017-02-23 15:32:31 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *dac_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dac_*_m* && IS_SEQUENTIAL}]
library/axi_dacfifo: Update the bypass logic The bypass logic is located between the AXI read controller and the DAC CDC fifo. When the bypass is enabled the DMAC destination interface must be clocked with the PL_DDR controller's ui_clk. This way it can easily switch between the AXI read's stream and DMAC's stream interface.
2016-06-22 09:24:54 +00:00
axi_dacfifo: Redesign the bypass functionality
2017-02-23 15:32:31 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *dac_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dac_*_m* && IS_SEQUENTIAL}]