diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v
index 30e3901c8..99b639e61 100644
--- a/library/axi_dmac/axi_dmac.v
+++ b/library/axi_dmac/axi_dmac.v
@@ -448,6 +448,7 @@ axi_dmac_transfer #(
   .DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
   .DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
   .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
+  .DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN),
   .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
   .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
   .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
diff --git a/library/axi_dmac/axi_dmac_burst_memory.v b/library/axi_dmac/axi_dmac_burst_memory.v
index a2cd5a26b..c05485d1f 100644
--- a/library/axi_dmac/axi_dmac_burst_memory.v
+++ b/library/axi_dmac/axi_dmac_burst_memory.v
@@ -43,6 +43,7 @@ module axi_dmac_burst_memory #(
   parameter ASYNC_CLK = 1,
   parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DATA_WIDTH_SRC/8),
   parameter BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST),
+  parameter DMA_LENGTH_ALIGN = 3,
   parameter ENABLE_DIAGNOSTICS_IF = 0
 ) (
   input src_clk,
@@ -143,10 +144,10 @@ reg dest_valid = 1'b0;
 reg dest_mem_data_valid = 1'b0;
 reg dest_mem_data_last = 1'b0;
 
-reg [BYTES_PER_BURST_WIDTH+1-1:0] burst_len_mem[0:AUX_FIFO_SIZE-1];
+reg [BYTES_PER_BURST_WIDTH+1-1-DMA_LENGTH_ALIGN:0] burst_len_mem[0:AUX_FIFO_SIZE-1];
 
 wire [BYTES_PER_BURST_WIDTH+1-1:0] src_burst_len_data;
-reg [BYTES_PER_BURST_WIDTH+1-1:0] dest_burst_len_data = 'h00;
+reg [BYTES_PER_BURST_WIDTH+1-1:0] dest_burst_len_data = {DMA_LENGTH_ALIGN{1'b1}};
 
 wire src_beat;
 wire src_last_beat;
@@ -217,7 +218,7 @@ end
 
 always @(posedge src_clk) begin
   if (src_last_beat == 1'b1) begin
-    burst_len_mem[src_id_reduced] <= src_burst_len_data;
+    burst_len_mem[src_id_reduced] <= src_burst_len_data[BYTES_PER_BURST_WIDTH:DMA_LENGTH_ALIGN];
   end
 end
 
@@ -295,7 +296,7 @@ end
 
 always @(posedge dest_clk) begin
   if (dest_burst_valid == 1'b1 && dest_burst_ready == 1'b1) begin
-    dest_burst_len_data <= burst_len_mem[dest_id_reduced_next];
+    dest_burst_len_data[BYTES_PER_BURST_WIDTH:DMA_LENGTH_ALIGN] <= burst_len_mem[dest_id_reduced_next];
   end
 end
 
diff --git a/library/axi_dmac/axi_dmac_transfer.v b/library/axi_dmac/axi_dmac_transfer.v
index d9afc7513..3f0b3863e 100644
--- a/library/axi_dmac/axi_dmac_transfer.v
+++ b/library/axi_dmac/axi_dmac_transfer.v
@@ -39,6 +39,7 @@ module axi_dmac_transfer #(
   parameter DMA_DATA_WIDTH_SRC = 64,
   parameter DMA_DATA_WIDTH_DEST = 64,
   parameter DMA_LENGTH_WIDTH = 24,
+  parameter DMA_LENGTH_ALIGN = 3,
   parameter BYTES_PER_BEAT_WIDTH_DEST = $clog2(DMA_DATA_WIDTH_DEST/8),
   parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC/8),
   parameter DMA_TYPE_DEST = 0,
@@ -317,6 +318,7 @@ dmac_request_arb #(
   .DMA_DATA_WIDTH_SRC (DMA_DATA_WIDTH_SRC),
   .DMA_DATA_WIDTH_DEST (DMA_DATA_WIDTH_DEST),
   .DMA_LENGTH_WIDTH (DMA_LENGTH_WIDTH),
+  .DMA_LENGTH_ALIGN (DMA_LENGTH_ALIGN),
   .BYTES_PER_BEAT_WIDTH_DEST (BYTES_PER_BEAT_WIDTH_DEST),
   .BYTES_PER_BEAT_WIDTH_SRC (BYTES_PER_BEAT_WIDTH_SRC),
   .DMA_TYPE_DEST (DMA_TYPE_DEST),
diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v
index 3ae9cf18f..3bd8dafe1 100644
--- a/library/axi_dmac/request_arb.v
+++ b/library/axi_dmac/request_arb.v
@@ -39,6 +39,7 @@ module dmac_request_arb #(
   parameter DMA_DATA_WIDTH_SRC = 64,
   parameter DMA_DATA_WIDTH_DEST = 64,
   parameter DMA_LENGTH_WIDTH = 24,
+  parameter DMA_LENGTH_ALIGN = 3,
   parameter BYTES_PER_BEAT_WIDTH_DEST = $clog2(DMA_DATA_WIDTH_DEST/8),
   parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC/8),
   parameter DMA_TYPE_DEST = 0,
@@ -939,6 +940,7 @@ axi_dmac_burst_memory #(
   .ASYNC_CLK(ASYNC_CLK_SRC_DEST),
   .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
   .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
+  .DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN),
   .ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF)
 ) i_store_and_forward (
   .src_clk(src_clk),
diff --git a/library/axi_dmac/tb/dma_read_shutdown_tb.v b/library/axi_dmac/tb/dma_read_shutdown_tb.v
index d1d0ec6e1..7d1b9e2ac 100644
--- a/library/axi_dmac/tb/dma_read_shutdown_tb.v
+++ b/library/axi_dmac/tb/dma_read_shutdown_tb.v
@@ -111,7 +111,8 @@ module dmac_dma_read_shutdown_tb;
     .DMA_TYPE_DEST(2),
     .DMA_DATA_WIDTH_SRC(32),
     .DMA_DATA_WIDTH_DEST(32),
-    .FIFO_SIZE(8)
+    .FIFO_SIZE(8),
+    .DMA_LENGTH_ALIGN(2)
   ) i_transfer (
     .m_src_axi_aclk (clk),
     .m_src_axi_aresetn(resetn),
diff --git a/library/axi_dmac/tb/dma_read_tb.v b/library/axi_dmac/tb/dma_read_tb.v
index 6e3f4a430..10b8d21d9 100644
--- a/library/axi_dmac/tb/dma_read_tb.v
+++ b/library/axi_dmac/tb/dma_read_tb.v
@@ -45,6 +45,7 @@ module dmac_dma_read_tb;
   `include "tb_base.v"
 
   localparam TRANSFER_ADDR = 32'h80000000;
+  localparam WIDTH_MAX = WIDTH_DEST > WIDTH_SRC ? WIDTH_DEST : WIDTH_SRC;
 
   reg req_valid = 1'b1;
   wire req_ready;
@@ -108,6 +109,7 @@ module dmac_dma_read_tb;
     .DMA_TYPE_DEST(2),
     .DMA_DATA_WIDTH_SRC(WIDTH_SRC),
     .DMA_DATA_WIDTH_DEST(WIDTH_DEST),
+    .DMA_LENGTH_ALIGN($clog2(WIDTH_MAX/8)),
     .FIFO_SIZE(8)
   ) transfer (
     .m_src_axi_aclk(clk),
diff --git a/library/axi_dmac/tb/dma_write_shutdown_tb.v b/library/axi_dmac/tb/dma_write_shutdown_tb.v
index af0379087..e299f3eec 100644
--- a/library/axi_dmac/tb/dma_write_shutdown_tb.v
+++ b/library/axi_dmac/tb/dma_write_shutdown_tb.v
@@ -113,7 +113,8 @@ module dmac_dma_write_shutdown_tb;
   axi_dmac_transfer #(
     .DMA_DATA_WIDTH_SRC(32),
     .DMA_DATA_WIDTH_DEST(32),
-    .FIFO_SIZE(8)
+    .FIFO_SIZE(8),
+    .DMA_LENGTH_ALIGN(2)
   ) i_transfer (
     .m_dest_axi_aclk (clk),
     .m_dest_axi_aresetn(resetn),
diff --git a/library/axi_dmac/tb/dma_write_tb.v b/library/axi_dmac/tb/dma_write_tb.v
index 6497327e7..17fcd4aaf 100644
--- a/library/axi_dmac/tb/dma_write_tb.v
+++ b/library/axi_dmac/tb/dma_write_tb.v
@@ -45,6 +45,7 @@ module dmac_dma_write_tb;
   `include "tb_base.v"
 
   localparam TRANSFER_ADDR = 32'h80000000;
+  localparam WIDTH_MAX = WIDTH_DEST > WIDTH_SRC ? WIDTH_DEST : WIDTH_SRC;
 
   reg req_valid = 1'b1;
   wire req_ready;
@@ -107,7 +108,8 @@ module dmac_dma_write_tb;
 
   axi_dmac_transfer #(
     .DMA_DATA_WIDTH_SRC(WIDTH_SRC),
-    .DMA_DATA_WIDTH_DEST(WIDTH_DEST)
+    .DMA_DATA_WIDTH_DEST(WIDTH_DEST),
+    .DMA_LENGTH_ALIGN($clog2(WIDTH_MAX/8))
   ) i_transfer (
     .m_dest_axi_aclk (clk),
     .m_dest_axi_aresetn(resetn),